Part Number: DP83867E
Hi,
We are using DP83867 in SGMII mode on a custom FPGA platform.
We observe that when a PC sends large Ethernet packets (jumbo frames) to the DP83867, the PHY asserts XGMII_ERR_INT (ISR register 0x0013, bit[2]) at 10 Mbps and 100 Mbps operation.
Observed behavior:
- PC -> DUT
- 10 Mbps: XGMII_ERR_INT asserted for large packets
- 100 Mbps: XGMII_ERR_INT asserted for large packets
- 1 Gbps: No issue observed
We would like clarification on:
1. What internal condition causes XGMII_ERR_INT to assert?
2. Is there a detailed status register that provides the root cause of the interrupt?
3. Does XGMII_ERR_INT correspond to:
- clock tolerance compensation (CTC) events,
- FIFO overflow/underflow,
- PCS alignment issues,
- MAC-side interface errors,
- or another internal condition?
4. Are there any known limitations or interoperability concerns related to large packet reception at 10 Mbps or 100 Mbps in SGMII mode?
1G
100M
10M
Any guidance on additional diagnostic registers to monitor would be appreciated.
Thank you.