TCAL9539-Q1: I2C spiketime

Bingyun Yang

Part Number: TCAL9539-Q1

Hi team,

Our customer is designing cockpit with our TCAL9539-Q1.
When the SCL signal is low, the SDA signal has a spike lasting 360ns. This duration exceeds the 50ns I2C spike time specified in the datashett.

But since SDA is low at this time, it probably won't affect the signal.

Since this spike occurs at the 9th clock cycle, we suspect it might be caused by voltage fluctuations during the transient switching between the master and slave in I2C communication.

I'd like to know if this spike has any potential risks, and if we want to reduce it, are there any specific measures we can take? Could you please help to give some advice? Thanks!

Best Regards,
Bryn Yang

2 days ago

+1 Tyler Townsend 1 day ago

TI__Guru 66488 points

Hi Bryn,

This looks like normal usage of the I/O expander during the 9th clock cycle, there is a handoff happening between master(controller) and slave(target). The controller releases the bus - the pullup resistor pulls SDA towards VCC, then some delay occurs, then the target pulls SDA = LOW. Thus you get a "spike." This is okay because it happens when SCL is low. SDA is allowed to change state during the low period of the clock.

Regards,

Tyler

0 Bingyun Yang 1 day ago in reply to Tyler Townsend

TI__Intellectual 1380 points

Hi Tyler,

Thanks for your explanation.

Best Regards,
Bryn Yang

0 Tyler Townsend 20 hours ago in reply to Bingyun Yang

TI__Guru 66488 points

Hi Bryn,

You're welcome. Please let me know if you have any additional questions.

Regards,

Tyler

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TCAL9539-Q1: I2C spiketime