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RESETN and OUT_ENABLE sequence and its importance

jeetendra y s
Prodigy 10 points

Hi,

I have USB3 link layer which is downloaded to FPGA.

Problem is, phy_status goes  LOW as soon as chip reset is asserted. Some time after de-assertion of chip reset phy_status goes high and remains continuously high thereafter.

I have attached the waveform.Please go through it and let me know if there are any issues. What could be the reason for this type of behaviour.

RESETN width is about 6us.8780.apple_new_1.pdf

Also i have some questions:

  1. Is there a certain sequence where RESETN to be followed after OUT_ENABLE or OUT_ENABLE to be followed after RESETN ?
  2. Is TX_CLK important during receiver detection operation  ?

Regards,

  • 0
    TI__Guru* 76130 points

    Hello, please see below my comments.

    --The PHY_STATUS is typically de-asserted 300us after RESETN has been de-asserted. Have you looked that far and it reamins active? Assert RX_TERMINATINO during reset (when RESETN is asserted).

    1.  Is there a certain sequence where RESETN to be followed after OUT_ENABLE or OUT_ENABLE to be followed after RESETN ?

    [ans] OUT_ENABLE and RESETN can be asserted at the same time, but OUT_ENABLE should be asserted only after 1.8V, it is not dependant on the other rails.
     
    2.  Is TX_CLK important during receiver detection operation  ?

    [ans] Yes, since PHY_STATUS has to be asserted for 1 clock cycle after detected a receiver.

    Regards.