I have two boards with a TUSB1310 and TUSB1310A USB 3.0 Transreciver. The board has a altera FPGA board in which i have downloaded our Usb 3.0 Core. I have connected all the
pins according the board specification. However the board with TUSB1310 's phy clk is nothing ,and the board with TUSB1310A can generate 250MHz on the pclk pin .
The strapping pins which needed to be set to '1' are pull up to 1.8v through 1K resistor.
We connect the RESETN to FPGA pin.
We connect the OUT_ENABLE to GND through 10K pull down resister,and connect to FPGA pin at the same time.
We generate the sequence of the reset through the FPGA.The FPGA holds OUT_ENABLE '0' for a while and de-assert it before the RESETN goes to high.
And how much time needed for the RESETN which keeps low??and the time between RESETN and OUT_ENABLE goes to high ?
Is there any special requirement for the TUSB1310 from the USB3.0 Pipe interface?
The 40MHz crystal generate 13.33MHz,we don't know the reason. and we use 40MHz osc.
If you have any idea,please let me know ASAP.
Thanks.
