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TUSB1310 phy_status

joey jiang
Prodigy 170 points
Other Parts Discussed in Thread: TUSB1310, TUSB1310A

Hi.

We are using TI's TUSB1310.We met a problem that the PHY can't generate the pulse on the  phy_status pin.

It kept low all the time.

We connect the OUT_ENABLE to GND through a 10K resistor.

We generate the reset sequence on the RESETN pin from the FPGA.

 How we connect the RESETN and OUT_ENABLE signal???

Please let me know if you have any idea ASAP.

Thanks.

  • 0
    TI__Guru* 76130 points

    Hello Joey,

    The RESETN has to be asserted by a minimum of 1us.

    OUT_ENABLE and RESETN can be asserted at the same time, but OUT_ENABLE should be asserted only after 1.8V is stable.

    If you connect OUT_ENABLE to ground then you are going to have all the I/O drivers disabled.

    One way to manage the OUT_ENABLE is to connect it to a 1.8V power on reset signal on the PCB, this can be a simple RC circuit connected to 1.8V rail where you are going to add a delay to the assertion of the OUT_ENABLE until the power rail is stable.

    Section 3 of the datasheet on the link below gives a good information about the reset and power on requirements.

    Regards.

    http://www.ti.com/lit/ds/symlink/tusb1310a.pdf