Reference Design for SN65LVDT41/14

Naveen,

Unfortunately we do not have a reference design for this particular set of devices (SN65LVDT14/41).  We do have general LVDS reference material at www.ti.com/LVDS that may help answer your questions about working with LVDS signals.

thanks,

Atul Patel

Texas Instruments

Naveen and Atul,

Here is the link to the LVDS products and design guides:

http://www.ti.com/ww/en/analog/interface/lvds.shtml

Regards,,nasser

Hello Atul and Nasser,

Thank you so much for the information. It did help me immensely to understand the LVDS products and application. 

However, I have a couple of questions regarding LVDS in general and SN65LVDT41 in particular. I am using two of SN65LVDT41 IC's to convert SPI Bus and 6 Chip Selects of the SPI Bus to LVDS to increase the distance of communication. I plan to use the SN65LVDT14 on the receiver side of the LVDS interface. 

1. I have read that an LVDS pair needs to be terminated at the destination/receiver with a 100/110 Ohm resistor between the two Differential signals. This means the single receiver on the SN65LVDT41 needs to be terminated similarly. I have done the same in my design. I need you to review/comment. I plan to terminate the other differential pairs near their destination i.e. SN65LVDT14 on the other side. Is this OK ?

2. I am not using the receiver interface of one of the SN65LVDT41's on my design. I have connected the differential input pins to GND. Is this termination fine ? If not, please suggest the right way to terminate the pins.

I am attaching the schematic page depicting the implementation. Please review and provide suggestions.

The differential pairs would be routed as controlled differential impedance of 100 Ohm with a GND/PWR layer beneath on the layout. Do you suggest any other points to be take care of during routing ?4370.SN65LVDT14_Sch.pdf

Thanks in advance,
Naveen 

Naveen,

You are correct that LVDS lines need to be terminated at the receive end of the transmission line.  However, for the SN65LVDT41/14 devices this termination is integrated into the chip already.  Because the termination is internal to the device, external termination should not be used.

It is OK to ground the unused differential inputs.  If you need the single-ended output to take on a particular value (high or low), you can use pull-up/pull-down resistors on the differential inputs to set a fixed differential voltage across them.  If you leave the single-ended output disconnected, though, this may be a “don’t care.”

I looked over the schematic.  It looks good, although the 100-Ohm resistors should be removed (as mentioned above).  If the supply voltages are fairly noisy, additional decoupling capacitances can be added to minimize the amount of noise seen by the LVDS transceivers.

The most important thing when it comes to the layout is to maintain the 100-Ohm differential characteristic impedance across the full length of the line.  This involves determining a particular geometry (line thickness, spacing, etc.) and then minimizing discontinuities.  Examples of discontinuities are connectors, 90-degree bends in traces, routing over a split ground plane, etc.  I’ve attached an application note that provides some detailed recommendations on how to ensure good signal integrity in a high-speed layout. 

7571.High Speed Layout Guidelines.pdf

Best regards,
Max Robertson
Analog Applications Engineer
Texas Instruments
m-robertson@ti.com

Naveen,

With respect to Max's comment regarding treatment of un-used LVDS inputs, there is an app note that goes into further details on this subject. Here is a link to this app note:

http://www.ti.com/lit/an/snla051b/snla051b.pdf

Regards,,nasser

Hi to every one!

I have to ask one thing about your configuration... I like to use SN65LVDT14/SN65LVDT41 to extend SPI interface like you. Can I connect one master to multiple slave with LVDS? In which way did you do it?

Thanks

Fabio

Hi Fabio,

This type of configuration is known as a multidrop configuration. Take a look at this application report from TI where the different variants of the LVDS standards are discussed: http://www.ti.com/lit/an/slla108a/slla108a.pdf

The differential input leakage current of the receiver is not specified in the TIA/EIA-644 (LVDS) standard which was later modified in the TIA/EIA-644A standard to be 6uA to support the multidrop topology.

The SN65LVDT14/SN65LVDT41 chipset is compliant to the TIA/EIA-644A standard so they can be used in this type of topology.