serializer deserializer for diffrential in out

Hi uzmeed, can you tell us the differential data standard coming from your ASIC?

Thanks,
RE

We don't have a perfect fit for your application, but there are a few different options which we can use depending on your needs:

The DS92LX1621/DS92LX1622 is a serializer/deserializer pair which will take a 14 bit wide data bus 15 50MHz and serialize to a single differential pair, then deserialize on the other side.

It does not meet your needs in that it has single ended LVCMOS inputs rather than differential, and the cable reach will not extend to your desired 20m as a native.  We can address the cable reach with the addition of a cable driver and equalizer such as the DS30EA101 and DS30BA101, which will extend the cable reach beyond your requirement, but you will still be faced with the need to convert your differential data to single ended with a product such as the DS90LV048.

Another possibility would be to use the DS92LV0421/ DS92LV0422 serdes pair.  These parts have differential input and outputs, will support your speed requirements.   The Serdes is only 4 bits wide, so you would need 4 of the parts to construct a wide enough bus, and you would then need.  You would also need to make sure that the received data is properly realigned at the receive end, if there is inter pair skew on your cable.  Cable length on this application is on the edge - the parts will work with up to 10m of cable at 75MHz, your running at a lower speed will allow for longer cable reach, and there are de-emphasis and equalization settings which will help to stretch the cable length further - 60ft may be doable, but you would want to confirm this yourself.

Hi Uzmeed,

Please describe the differential output format as Ross had requested. TI has several devices that may work, including some new devices that are sampling now.

Mike Wolfe

DPS APPS / SVA

Hi

the data is 14 bit wide LVDS . 

regards

uzmeed

Hi

I hav read the data sheet for DS92LV0421 if i use 4 iCs with same clock will these Ics be synchronized with each other ???

regards

uzmeed

Greetings -

As Ross and Mike noted, please advise more on your 14 differential data buts from the ASIC. How fast are these, are the LVDS, how are the clocked?  Knowing this, then one can determine if or how to serialize.  For example, it might be best to convert to Single-ended with LVDS receivers and the serialize into one high speed stream with a DS92LV2421.  The DS92LV0421 expects 4 channels of LVDS with a 7:1 format.  it is not a solution to use 4 of them to get 16 inputs.

John Goldie

DPS APPS

Hi uzmeed,

"the data is 14 bit wide LVDS" - so do you have 28 wires (14-lanes) used for data?  How many wires are used for clock?

I believe the DS92LV0421 requires the frequency of the data to be 3.5x the clock frequency (7 bits per clock period).  Is this what your ASIC outputs?

Best regards,
RE

Uzmeed

The outputs of the four transmitters will be synchronized with one another, but you indicated that you wanted to transmit over 20m of cable, and it is quite likely that 20m of cable will have enough pair-pair skew such that theoutputs of the four receivers may not be synchronized.   In order to minimize pair-pair crosstalk on cable, manufacturers often have different twist rates for the different pairs on a cable which can induce pair-pair skew.   To deal with this you can either try to resynchronize the four blocks of four bits at the receive end, or you can try to match the delays on the cable through careful cable choice.

Mark Sauerwald

Mark, I haven't heard of different twist rates.  If the differential data lanes are transitioned and sampled at the same time, you'd want them all in sync, so that all crosstalk impacts lanes near the transition and not near the middle sampling time.

Best regards,
RE

Hi

Thanks to all of u for ur encouriging response

the complete data that is to be transmitted is  14 bit diffrential data (28 lanes) , 1 bit diffrential data for "bad data flag" (2lanes) 1 bit diffrential data for "valid data flag" (2 lanes).

The external differential clock of 50 MHz is provided to the module .

1 differential input is Ext_trigger ( 2 lane) and one pin for DGND

the output is connected to the 37pin D type connector.

And as i mentioned earlier that data format is LVDS

regards

uzmeed

Greetings

It sounds like you have a 14-17 bit wide LVDS bus that is about 50MHz.  There are a couple of SER/DES that collect LVDS data (but in a different format / width) and reduce down them to a single high speed line.  These will not be compatible with what you have.  I see two options for you to research:

a) you could use a FPGA to built a SER/DES function based on your unique LVDS bus width / rate.

b) you could convert the LVDS back to single-ended (DS90LV048A quad receiver, or there are other parts as well, e.g. SN75LVDS386 (16CH REC)  ) and then SERIALIZE that up with a DS92LV2421 and DS92LV2422 for example. 

That would be my best recommendations to your application.

John Goldie
DPS APPS / SVA

Thank u all of u

I m trying to implement it in FPGA . I will let u know when i will get some results.

Regards

uzmeed

Hi John Goldie,

                       This is Karun from Asmaitha Wireless Technologies (P) Ltd. Bangalore,India.In one of our project RGB to LVDS interface,we used #DS90CF383B TI chip,for converting RGB signals to LVDS. We fed that signals to a LVDS display having resolution 1280*800,but problem is that only quarter of the screen is coming.Please help us on this issue.

Looking forward to hear from you.

Thanks,

Karun

Asmaitha Wireless Technologies (P) Ltd.
Bangalore-40 

Karun

What is the source and format of your RGB data, and when you displayit on the panel, you say that only 1/4 of the screen is coming, can you be more specific on what you see? - Is there a full image on 1/4 of the panel, is only the red being shown, is every other pixel on every other line being shown etc.   A better understanding of your issue will help me to find a resolution to it.

Mark