As I dig into the datasheet for the 65LVDS84, I see what appears to be an error. The Switching Characteristics table on page 5 lists a set of delay times (td0, td1, etc.), which are defined as delays from CLKOUT's rising edge, and refer to Figure 6. Figure 1 (page 6) is consist with the idea that the new cycle of data output starts after the rising edge of CLKOUT. However, Figure 6 (on page 9) shows those times referenced to the falling edge of CLKOUT. Is Figure 6 incorrect?
Thanks,
Scott
