Tech Support,
Customer is rying to bring up a new platform with the xio2001 under Linux, and running into a few questions about the bridge.
For example, we're seeing the following PCI configuration space:
21:00.0 Class 0604: Device 104c:8240
Flags: bus master, fast devsel, latency 0
Bus: primary=21, secondary=22, subordinate=22, sec-latency=0
Memory behind bridge: 00100000-001fffff
Capabilities: [40] Subsystem: Device 0000:0000
Capabilities: [48] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+
Capabilities: [70] Express PCI/PCI-X Bridge, MSI 00
Capabilities: [100] Advanced Error Reporting
00: 4c 10 40 82 06 00 10 00 00 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 21 22 22 00 f1 01 a0 22
20: 10 00 10 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00
We believe the 0x22 at offset 0x1e is the secondary status register.
This value seems to indicate that a master abort has been received.
But the bit never seems to clear, even though it appears to be a clear on read bit.
Are we interpreting this correctly? And if so, why does the error bit never clear?
Mark Ackerson
Texas Instruments
Field Applications – MCU Products
(612) 991-1215 (Cell)
mark.ackerson@ti.com
