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TUSB1310A jitter on PCLK

Elmar Stahleder
Prodigy 60 points
Other Parts Discussed in Thread: TUSB1310A

Hi all,

I notice an jitter on PCLK (250MHz).

The TUSB1310A is running with  a reference clock of 40MHz and the strapping option-pins for 40MHz are set. All the different power sources are clean. The 40MHz ref-clock and the 60MHz Ulpi-Clock are clean.

Only the 250MHz clock has a frequency jitter. After around 100 clocks (400ns) the clock edges have an jitter of around 2ns.

Has anyone else noticed such jitter? Is this amount of jitter OK?

Is there a special reset sequence required to initialize the chip internal PLL? My current sequnce is to release RESETN first then PHY_RESETN.

Best regards, Elmar

  • 0
    TI__Guru* 76130 points

    Hello Elmar,

    The sequence for RESETN is that all the power supplies and the Reference Clock must be stable before the de-assertion of RESETN, de-asserting PHY_RESETN after RESETN is OK.

    The 2ns jitter is not OK, it should be in the order of  tens ps. Are you connecting PCLK to TX_CLK?

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 60 points

    Hello Elias,

    thank you very much for your quick response.

    Ref-Clock and power supplies are stable for sure. Yes PCLK is connected to TX_CLK.... is this a problem? I already tried to cut all PCLK connections but the jitter remains. My application is an USB3 trace which records the USB3 activity between host and device. Only the RX path of th TUSB1310A is used. To set the TX path in 'passiv' mode all TX-data lines are grounded and TX_CLK is connected to PCLK. Could this setup cause trouble on PCLK?

    Questions:

    - Which power pins are related to the chip internal PLL. Which other pins can have an influence on PLL function (the manual is not very precise on this)

    - Is it possible to check if the RefClock strapping option is sampled correctly (e.g. status register).

    Regards, Elmar

  • 0 in reply to Elmar Stahleder
    TI__Guru* 76130 points

    Hello Elmar,

    Connecting PCLK to TX_CLK is correct. I am not sure what you are referring to with "only the RX path of the PHY..." for a communication between a host and a device it is required that both devices transmit and receive data. Are you using the TUSB1310A on your host or on your device?

    Anyway, I don't think this could be affecting PCLK. The voltage pin for the PLL is C12 and the ground pins are VSSA.

    I will ask if someone had seen this.

    Regards.