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TL16C754C:How to set TLR regsiter in TL16C754C controller

Other Parts Discussed in Thread: TL16C754C, OMAP-L138

Hi,

We are using TL16C754C controller.

How can we dump the readable registers of the controller and how to set the TLR Register to get interrupt for every 4/8/12/16/32 bytes while receiving the data.

Currently the interrupt was generating for each and every byte.

We are using CPU mode of transfer to read data from UART and DMA being not used.

We also observe that while writing to THR register we need put a delay between each register write.

Do we have to maintain a 85nS delay between each register write as specified in timing diagram (t15d and t9d)?

Apart from these the initialization sequence given in TL16CP754C/TL16CM754C/TL16C754C Programmer's Guide page do we have to follow the same sequence.

Because at driver level some of the events may need to be set at different levels.

Thanks for you time and reading the post.

Regards,

GSR.

  • hello all,

    any suggestions.

    regards,

    GSR

  • GSR,

    To access the TLR register you must first set EFR[4]=1 and MCR[6]=1.

    Some delay may be required before reading the THR because it takes some time for the serialization of the data and for the transmitter status bits to update in the LSR. For the standard registers you can program them in any order but some enhanced registers like the TLR require bits to be set in other registers before you can access them.

    To dump the readable registers you can use the inportb command

     

    /* Comm Port 1 or A -- UART register set definition */
    #define RBR_UART1      0x300  /*Receiver Buffer Register of chA */
    #define THR_UART1      0x300  /*Transmitter Holding Register of chA */
    #define IER_UART1      0x301  /*Interrupt Enable Register of chA */
    #define IIR_UART1      0x302  /*Interrupt Identify Register of chA */
    #define FCR_UART1      0x302  /*FIFO Control Register of chA */
    #define LCR_UART1      0x303  /*Line Control Register of chA */
    #define MCR_UART1      0x304  /*Modem Control Register of chA */
    #define LSR_UART1      0x305  /*Line Status Register of chA */
    #define MSR_UART1      0x306  /*Modem Status Register of chA*/
    #define SPR_UART1      0x307  /*Scratch Pad Register of chA */
    #define DLL_UART1      0x300  /*Divisor Latch LSB of chA */
    #define DLM_UART1      0x301  /*Divisor Latch MSB of chA */
    /* End Comm Port definition */

     

    main(
     

     // read registers 
     /* Port 1 - Channel A */

     inportb(LCR_UART1);         /* read RHR*/
     outportb(LCR_UART1, 0x00)   /* set LCR[7]=0 */
     inportb(IER_UART1);         /* read IER*/
     inportb(IIR_UART1);         /* read IER*/
     inportb(MCR_UART1);         /* read MCR*/
     inportb(LSR_UART1);         /* read LSR*/ 
     inportb(MSR_UART1);         /* read MSR*/     

     inportb(SPR_UART1);         /* read scratch pad register*/
    }
    /* end of main */

    My bench setup uses MS-DOS so I can directly access the registers with debug commands and scripts.

    Best Regards,

    Joe

  • Hi Joe,

    Thank you for the reply and your time.

    For example we are using EMIFA Interface available on TI's OMAP-L138 processor. EMIFA doesn't support inserting delays if the current write/read operation was precding directly by another write/read operation.

    What about the Read Cycle Delay(t9d) and Write Cycle Delay (t15d)?

    These delays are required between a read and a write or these to be maintained between consecutive writes/reads?

    Regards,

    GSR

  • GSR,

    t15d is the minimum time after /IOW goes high (deasserts) before it can be asserted again for the next write cycle.

    t9d is the minimum time after /IOR goes high (deasserts) before it can b e asserted again for the next read cycle.

    Best Regards,

    Joe