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TFP403 Data Setup and Hold Time

mike stone
Prodigy 80 points

Other Parts Discussed in Thread: TFP403

Hi,

    I am confused by    Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK  on page 9 of TFP403 datasheet.     tsu(1) & th(1) are 1ns on page 8.  How to figure out when the outputs are valid & stable?   I mean data can not be valid only 2ns + clk tf !!!   all output are latched on clk falling or rising edging right!!  

  • 0
    TI__Mastermind 20985 points

    Hi Mike, sorry for the delay in responding.  The "1ns" refers to the minimum setup/hold.  This is conservative and is worst-case at the fastest frequency (165MHz).  It is true across temperature, voltage, and semiconductor process variation.  We have measured a typical setup/hold of 2.1/2.4ns on one device.  This becomes longer at slower frequencies; at 25MHz, typical can be 16/20ns.  These values also depend on the rise/fall time, which depends on the capacitive load that the output drives.

    Yes, all output data is latched on either the rising or falling clock edge, depending on "OCK_INV".

    Best regards,
    RE