This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CABLE DRIVER+ EQUALIZER

Guru 13485 points
Other Parts Discussed in Thread: LMH0344, LMH0303

3005.HYPERLYNX-OSCOPE_ti.pdf5807.hyprelinx_sim_ti.pdfWe are considering to use TI LMH0303 (cable line driver) and LMH0344(Cable equalizer).

During pre-layout simulation by using hyperlinx , I encounter that the received signal at the equalizer has some DC above Vcm, when we run the signal above 2Gbps.

My question is, What is the permitted signal at the receiver(In other words, what is VinH and VinL).

The  file "hyprelinx_sim_ti (2).pdf" demonstrates  the simulation that I did.

The file " HYPERLYNX-OSCOPE_ti (3).pdf" demonstrate the results that we got.

  • We have characterized the devices with HD-SDI signals, the HD-SDI specification allows for 50mV of DC shift on the signal.   If I understand your hyperlynx simulation, it looks like you might be anticipating significantly more than this.  It is not clear to me if the shift on the Hyperlynx plot is a startup condition since the LMH0344 will bias the input itself, and the time constant set by the combination of the 1.0uF cap and the LMH0344 input impedance is significantly longer than the timebase on your simulation.