We have been seeing some strange behavior out of the PCIe devices so we started looking at the registers and the values that get written into those registers, trying to see if we can figure out what the switch is doing. What was observed is that some of the registers seem to want data in little endian and others appear to want it in big endian.
For instance, when writing one register with data like 14 60 then read it back, it comes back as 14 60. When writing the next register with 90 30, it comes back 30 90. Using the SEEPROM contents sent to us earlier, we cannot do some things with the chip and the belief is that the chip isn’t getting set up properly. After accommodating some of the endianness oddities, we can now make the chip work properly, or at least more predictably.
Is there some document that we don’t have that describes the observed behavior? Can you provide any insight into why the chip is responding as it is?
