power and signal wires design between tow PCB borad

I guess we are talking about digital boards. You don't need to power them by the same power supply, as long as it is the same type (i.e., both of them 5V+- tolerance). Even when they are of diferent voltages, it can be solved, but it is not your case.

The rise time of the signals to pass thru the connectors is important. Also the type, it is not the same serial buses than parallel buses, synchronous than asynchronous. If you have clock signals or sensitive analog signals in the connector, they need special care. It is not the same single ended than differential signals... etc.

You should give more details of the type of signals shared between the boards. Consider the big differences between an RS232 connection, a PCI connection, and a PCIe connection. All those protocols frequently connect between two boards.

The issue we are talking of is called signal integrity. Signal integrity depends on the rise time of the signals on the bus and the length of the bus. Depending on the relationship between rise time and length of a wire, the wire behaves as a simple cable or as a transmission line. When the connection is a transmission line, you have to adapt the impedance of the devices to the bus, so there won't be reflections, overshoot, undershoot, ringing, etc.

It is a lengthy issue to cover in a single post in a forum. I can only give you some guidelines.

If your bus is synchronous and you are working at frequencies of up to 50MHz, you can look at the PCI specifications to adopt guidelines for layout, signals on the board, location and mapping of signals on connectors, etc. If you are trying to work at frequencies much higher than that, it is almost imperative for you to hire an experienced consultant.

Thank four your reply.

The frequency of board is 12M.

May I consider the Signal Integrity Problem is caused by PCB layout?

I want to know that can I connect the data bus and address bus directly to the FPGA pin, or shout I place opto-isolators in the data bus?

Thanks.

If that is the frequency of the data going in the bus, it is not very difficult to let them go through. Anyway, put at least a series resistor for each line of the bus. For output signals, a 33 Ohm resistor close to the output of the device. For bidirectional lines, a 33 Ohm resistor in the middle of the line. You don't need optocouplers. Many FPGA have option for activating terminations inside the die, check if it is your case. On your connector, try to put one ground pin for each two signals. Take a look at a PCI specification, signals on a connector are ordered like this:

 SIG      GND

GND      SIG

SIG        SIG

SIG       GND

GND    SIG

... etc.

This way, each signal has at least one GND as neighbour. Try to read a book about signal integrity, to learn about design and layout considerations for digital buses. Do you know how to design the stackup of a PCB? Did you search for reference boards similar to yours? Learn them, and look at their layout. Good luck.

First of all, good election for a book. It can be a bit tough on the math side, but it is definetly the bible for S.I.

As you may know, single ended lines are typically designed to be 50 Ohm on FR4 PCB boards. You want to make the impedance of your driver to be close to the 50 Ohm of the bus, to match impedances. A typical resistance output of a CMOS driver is in the order of 20 Ohm, added to the 33 Ohm, you achieve 50 Ohm.

When you make higher speed designs you don't go by this "thumb" rules and you use IBIS models that represent the exact output characteristics of your buffer. Anyway, you can always check your data lines and change this resistor value a to a larger value if there is ringing, or a bit lower if your signal rise time is too slow. But for your application you should be OK with that value.

Good luck!

It is to "match impedance", meaning, to make the impedance of the driver equal to the impedance of the transmission line, and the impedance of the receiver also equal to that of the transm. line. When impedance is matched, power transfer is maximum and there are no reflections.

The characteristic impedance of a loss-less, ideal transmission line, if terminated with its characteristic impedance z0, is equal to z0, and this is true for any length of transmission line:

http://en.wikipedia.org/wiki/Transmission_line#Input_impedance_of_lossless_transmission_line