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DP83640 Evaluation Kits

Eryk Druszkiewicz
Prodigy 20 points
Other Parts Discussed in Thread: DP83640

Good day,

Due to somewhat surprising answer from support@ti.com I was invited to post my question here.

We are working on incorporating the IEEE1588 into our designs. We saw the "DP83640 10/100 IEEE 1588 Time Sync Demo by Alex" and got interested. We wanted to buy the ALP100 used in the demo by Alex, but it seems that it is not sold anymore(?). From the documentation it seemed like ALPNano which is on each of the DP83640 is an alternative to the ALP100. Thinking that ALPNano will be able to emulate what the ALP100 did in the demo we bought two of the DP83640 Evaluation Kits hoping to recreate the synchronization demonstration. 

Now when the boards came it looks like using National Analog LaunchPAD software I have limited control over the boards and am not able to do something meaningful/similar to the demo (seeing how the clocks get synchronized). Would you be so kind to let me know how I can use the boards to do something meaningful out of the box without much development work? Or would I need to develop a host controller that would induce the PTP traffic? If the ALP100 board is necessary, where can I buy it or even better would it be possible to borrow one (with some kind of security deposit)?

Thank you for your time and assistance,

With regards,

Eryk D

  • 0
    TI__Mastermind 31600 points

    Eryk,

    The ALP100 board is not available for sale. I will provide some details on the Eval Kits below.  In the meantime, could you please provide some details of your goals for your evaluation?  That might help me in providing you with the right information and determining how we might be able to help.  I am interested to know what level of synchronization accuracy you require, what your end application is, what level of software development you would undertake for the development, etc.

    The DP83640T-EVKs provide hardware assist for IEEE 1588, but they do not perform IEEE 1588 PTP synchronization by themselves.  In the demo, an IEEE 1588 PTP stack is running in software on a PC.  The FPGA on the ALP100 board provides MAC functionality, packet buffering, etc.  The DP83640 devices perform packet filtering and timestamping for IEEE 1588 as well as clock generation, event monitoring, output triggering, etc.

    The DP83640 device does support a Synchronous Ethernet mode that can be used to evaluate synchronization between the two devices.  No time or phase information is shared between the master and the slave, but you can do a comparison of frequencies for the devices, somewhat similar to what is done in the demo.  Would that be of interest to you?

    As I mentioned, if you can provide some guidance on your end goals and expectations, we can try to help you find a solution.  Hopefully we can still find a way to help you realize your solution using our devices.

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 20 points

    Good day Patrick,

    Thank you very much for your reply. Our application is scientific instrumentation. We are looking at many different options of obtaining frequency and phase synchronization under 100ps.

    At this point in time as we are evaluating different approaches we want to limit the time spent on software development to the necessary minimum, but once a promising approach is found we are ready to do low level development.

    I actually did get the Synchronous Ethernet to run earlier on the demo boards and got a very nice first result of period stability between the two clocks of <92ps over many hours. As you noted the phases do not get aligned but they are locked with a random phase offset.

    In the data sheet I found this register: FREE_CLK which can have the following values:

    1 = RX_CLK is free-running.
    0 = RX_CLK phase adjusted based on alignment.

    I tried to find the meaning of "RX_CLK phase adjusted based on alignment" in the datasheet and could not find an explanation. Did I miss it somewhere? Is it referring to alignment obtained with IEEE 1588 PTP? Putting the two boards (appropriately interfacing the PHY) in series between a PTP master and slave stack and keeping the FREE_CLK at "0" while Synchronous Ethernet is enabled would result in phase and frequency synchronization?

    The video shows that the clocks get synchronized to about 3.8ns (1 sigma) with an Xtal 25MHZ. Are you aware of any potentially better results obtained with a better clock source (like TCXO, OCXO )?

    Thank you for your time and assistance,

    With regards,

    Eryk

  • 0 in reply to Eryk Druszkiewicz
    TI__Mastermind 31600 points

    Eryk,

    The IEEE 802.3 specification allows the RX_CLK to be held for part of a period after a link is achieved to align the signal to the RXD data.  This is considered normal operation for RX_CLK.  Setting the FREE_CLK bit prevents this phase alignment.  Default operation, where RX_CLK is phase aligned, adheres to the IEEE specification and is the preferred configuration.

    Synchronizing the PTP Slave to less than 10ns (1 sigma) relative to the PTP Master is a realistic result.  The impact of using a TCXO or OCXO will be on long term synchronization.  Environmental effects on the XO can cause the frequency to drift relative to the PTP Master reference clock.  Using a TCXO or OCXO can reduce that effect. 

    Patrick