DP83848CVV revision

André,

Could you provide a schematic for review?  If you would prefer not to post it to the forum, you could email the schematic to me directly at patrick.ofarrell@ti.com. 

In the meantime, could you provide some details on the nature of the problem you are seeing?  What happens when the boards fail to work properly?  Do the boards link?  Do they transmit and receive packets correctly?  Do the LEDs correctly indicate the link, speed, and activity?

Patrick

Hi Patrick,

did you get my email?

Regards,

Andre

André,

I have partially reviewed the schematic.  I will complete a more thorough review when time permits, but I believe I have identified at least part of the problem. 

The 25MHz_OUT pin from the DP83848 should not be used as the RMII reference clock for the processor/MAC.  This pin will output a 50MHz clock in RMII mode, but the output clock is a simple buffered version of the input clock.  We cannot guarantee the timing of this output clock relative to the RMII data.  This connection is most likely the cause of the issues being seen.  

The preferred connection would be to source the clock to both the processor/MAC and the Phy directly from the 50MHz oscillator.  I would suggest attempting this modification on a failing board via a jumper wire to see if it resolves the issue.

Our RMII application note, AN-1405 (Literature Number:  SNLA076) , explicitly states that the 25MHz_OUT pin from the DP83848 should not be used as the RMII reference clock.  I have quoted the text below for your reference:

The 25MHz_OUT signal is a delayed version of the X1/
REF_CLK input. While this clock may be used for other
purposes, it should not be used as the timing reference for
RMII control and data signals.

The direct link to the application note is:

http://www.ti.com/lit/an/snla076/snla076.pdf

Having noted that, I believe that the datasheet would benefit from the addition of some text to make this connection more clear.  I will update the datasheet to do so.

Patrick

Patrick,

the test would be only connect pins 34 and 25?

Why the boards work with older versions of the PHY? And the enginner that designed this circuit has done like this in all his projects with no problems so far...

Anyway, I'm looking forward to hearing from you about your more thorough review.

Thanks,

Andre

Andre,

I am sorry.  I was not very clear in explaining my proposed experiment. 

What I am recommending is to disconnect the DP83848 25MHz_OUT (pin 25) by cutting the board trace or lifting the package pin.  Then connect the oscillator output (pin 3) directly to the RMII reference clock input (pin 126) of the processor/MAC using a jumper wire.  The board trace from the oscillator output (pin 3) to the DP83848 X1 input (pin 34) does not need to be modified.  In this way, the same 50MHz clock will be provided to both the Phy and the MAC.  The intent is to improve the RMII timing and prevent any packet errors.

The delay through the DP83848 from the X1 input to the 25MHz_OUT output can vary from device to device.  Variations in this delay, along with variations in package parasitics, board traces and capacitance, supply voltages, temperature, etc. can all impact the RMII timing. 

Patrick

Patrick,

I did the jumper without lifting pin25 (25MHz_OUT) and it worked fine.

However, as a definitive solution, I will ask the technician to do as you said.

I will let you know tomorrow, after I perform some more tests.

For the pcb lay-out review, what should I do with 25MHz_OUT? Just leave it disconnected? Or should I put a pull-up of some kind?

Thanks,

André

Thanks Patrick,

the boards are ok after this change.

Andre