TFP410 not displaying Video

Chander Shekhar Rana

Other Parts Discussed in Thread: TFP410

Hi,

With regards to the discussion at below location, I would like to put my concern also.
(http://e2e.ti.com/support/interface/digital_interface/f/130/p/135008/691644.aspx#691644)

My logic is also not working when I want to drive DVI Monitor.

In my schematics TVS410 is attached with FPGA in below configuration:
ISEL --> Pulled HIGH for I2C mode enabled
PD --> Grounded
IDCK- --> Grounded
IDCK+ --> 40Mhz clock

On startup;
Writing the default in CTL_1_MODE register; value=0xFE

Below is other register setup
-- --
DE_DLY --> H'64
DE_CTL --> H'30
DE_TOP --> H'4B
DE_CNT --> H'0320
DE_LIN --> H'0258
H-RES --> H'0384
V-RES --> H'02A3

After this I am reading the Values of above registers,
The read value are:
-- --
DVI DE_DLY = 0x64
DVI DE_CTL = 0x30
DVI DE_TOP = 0x4B

DVI DE_CNT Lower = 0x20
DVI DE_CNT Higher = 0x03

DVI DE_LIN Lower = 0x58
DVI DE_LIN Higher = 0x02

DVI H-RES Lower = 0x5E
DVI H-RES Higher = 0x03

DVI V-RES Lower = 0x67
DVI V-RES Higher = 0x02

After this writing value in CTL_1_MODE register; value=0xB5

Below is behaviour on Monitor attached with the board:
when FPGA programed, but register not configured --> Cable Not Connected
FPGA Programmed and register configured --> Blank screen

If I change some value of H-RES, DE_DLY, V-RES etc to some other value, Monitor shows --> data not supported.

I have put the schematics of TVS410, wave forms of HSYNC, VSYNC, and DE, on web. Please follow the link to see the listed files.

https://docs.google.com/open?id=0BxS03ak_35ixYzlld1dQcERhZjA
https://docs.google.com/open?id=0BxS03ak_35ixSWhzU3pVSlUta2s
https://docs.google.com/open?id=0BxS03ak_35ixNGw0M2swaVBtRkk

In the data port I am giving some constant values.

Regards,

Chander

over 13 years ago

0 Elias Villegas M. over 13 years ago

TI__Guru* 76130 points

Hello Chander,

The logic captures are good, but it will be more helpful if you have some taken with an analog scope.

Are you using the DE Generator function? Can you include the panel specs.

Please check the TMDS signals, can you take a scope capture of the output clock?

Regards.

0 Chander Shekhar Rana over 13 years ago in reply to Elias Villegas M.

Prodigy 30 points

Hello ELIAS,

Below is link for waveform taken on Scope:

https://docs.google.com/open?id=0B_65Ob5I2S_JR29RbjNjd0EzRzQ
https://docs.google.com/open?id=0B_65Ob5I2S_JS2h1dmR2ZzNVQ3M
https://docs.google.com/open?id=0B_65Ob5I2S_JSmx4Tk15X0xkNWM

In my logic I have given below parameters:

DE_TOP   = 75; -- Vertical Blanking Period / Pixel Blanking
DE_DLY   = 100; -- Horizontal Blanking Period / Line Blanking
DE_CNT   = 800; -- Valid Pixels per line
DE_LIN   = 600; -- Valid Lines per Frame
H_RES   = 900; -- Valid Pixels + Blanking Pixels
V_RES   = 675; -- Valid Lines + Blanking Lines

By following way I am generating the waveforms:
Generating VSYNC first,
Within VSYNC, generating 675 HSYNC,
After gap of 75 HSYNC started generating DE signal,
DE signal has width of 800 Clocks,
DE signal started 100 clock later than HSYNC.

Do my above assumptions are OK or WRONG

ONE more strange thing I observed, I am configuring H_RES by value 0x0384 but read back value of the register give the value 0x035E.

Regards,

Chander

0 Elias Villegas M. over 13 years ago in reply to Chander Shekhar Rana

TI__Guru* 76130 points

Hello Chander,

I've been out of the office long time.

The tFP410 just encodes the receiving signals into TMDS streams, the timing of the DE, HSYNC and VSYNS is very critical for the panel, so you need to go to the panel specifications to understand what is the required timing.

What is your clock frequency? Have you tried to change the clock frequency? Does the problem occur with different resolutions?

I've just took some scope captures of the control signals so you can have a background to compare the timing on your system, the attached file shows some captures of a working unit.

Regards.

5582.TFP measurements.docx

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TFP410 not displaying Video