In one of our design, we have two boards (VMC board & UI board). Both are connected through a ribbon cable of 1' and 1m length.
VMC board has iMX283 processor with 24bit RGB interface connected to TI LVDS transmitter (SN75LVDS83A) and LVDS signals are terminated in connector
UI board has 24bit RGB LCD connected to TI LVDS receiver (DS90C3202) and LVDS signals are terminated in connector
We had previous version of both the boards where we used only parallel interface, no LVDS transmitter/receiver was used. This setup works fine.
From the datasheets of transmitter & receiver, we understand that there is no specific software changes required for implementing LVDS link using these chipsets. The setup should work as it is. But we see a problem in getting the proper display. On LCD, we get distorted display refer attached image.
Following are for your information
- Processor is sending out LCD data on rising edge of clock (12Mhz)
- LVDS transmitter CLKSEL pin is configured for rising edge
- LCD panel is expecting LCD data on rising edge of clock
- LVDS receiver RFB pin is configured to rising
From our debugging, we have the following observation
- The input clock on transmitter IC and the output clock on receiver IC are of same frequency, but they are phase shifted (delayed). We are running clock at 12MHz and we are getting phase shift of 220nS.
- We checked all the input data at transmitter (LVTTL) and its corresponding output data at receiver (LVTTL). All of them are same in pattern and 220ns time difference, except few signals for which patterns are not same. These few signals are across LVDS pairs. So we can’t suspect one or two signal in pair.
Pls. suggest us how to debug further on this
Few questions we have on TI devices:
SN75LVDS83A
- If we keep CLKSEL pin of transmitter at high, what will be the phase difference between its input clock and its LVDS output clock. Similarly what will be the case if we keep CLKSEL at low.
- On which edge (rising or falling) of which clock (input single ended clock or output differential clock), the input data will be fetched in for doing parallel to serial conversion inside Transmitter.
Let us know this for both CLKSEL=1 and CLKSEL=0
DS90C3202
- On which edge (rising or falling) of which clock (output single ended clock or input differential clock), the output data will be sent out in receiver.
- On receiver datasheet, there is a term receiver propagation delay (RPDL) and is mentioned as “4*RCLKOUT” unit “nS”. How should we do this calculation? Either 4*time period of RCLKOUT or 4*frequency of RCLKOUT
