LMH1982 - PLL Lock Detection

Hi Kawai-san,

Sorry, the link I sent was for an internal website.  Here are some answers to your questions:

Lock Detection for PLL1
The phase differences between phase detector (PD) inputs produce different up/down output pulses to drive the charge pump and servo the loop filter / VCXO control voltage.  When the PLL is in a "locked" state, the up/down pulses will present equal pulses with minimum width to the charge pump inputs.  For PLL1, the up/down pulse width is compared against the time window (delay circuit) programmed via LOCK_CTRL register.  When the pulse width is within the window for 3 consecutive PD cycles, then valid lock is indicated (SD_LOCK = 1).  When the pulse width is outside the window for 3 consecutive PD cycles, then loss of lock is indicated (SD_LOCK = 0).

Lock Detection for PLLs 2/3/4
The phase differences between the PD inputs produce different up/down output pulses to drive the charge pump and servo the internal loop filter/VCO control voltage.  When the PLL is in a "locked" state, the up/down pulses should be equal with minimal width to charge pump inputs.  For PLLs 2/3/4, the time window is based on 2 inverter delays (~50 ps window, default), but this can be programmed to 6 inverter delays (~150 ps window) via a Reserved register 0x1Ch[bit 2].  Valid register values are 0x00h (2 inverter delays) or 0x04h (6 inverter delays).  When the pulse width is within the window for 3 consecutive PD cycles, then valid lock is indicated (SD_LOCK = 1 for PLL4, or HD_LOCK = 1 for PLLs 2/3).  When the pulse width is outside the window for 3 consecutive PD cycles, then loss of lock is indicated (SD_LOCK = 0 for PLL4, or HD_LOCK = 0 for PLLs 2/3).

Regards,
Alan