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xio2001 can't r/w prefetchable memory region of pci device

Yuan Gao1
Prodigy 30 points
Other Parts Discussed in Thread: XIO2001, TMS320C6415, TMS320C6414, TMS320C6416, TMS320C6205

In my design,  I didn't connect eeprom and xio2001 using default registers value (linux system configuration, kernel verison 2.6.32)

My platform is x86. I can see xio2001 bridge and pci device(DSP c6205) behind xio2001 by using lspci.

The question is I can't access prefetchable memory region of pci device, data reading from memory region is always 0xFFFFFFFF.

But I can access I/O region and non-prefetchable memory region of pci device.

If I lost config some register ?

Best regards.

  • 0
    Prodigy 30 points

    prefetchable and non-prefetchable test failed

  • 0
    Guru 317370 points

    Please show the output of "lspci -vvv" for both devices.

  • 0 in reply to Clemens Ladisch
    Prodigy 30 points

    02:00.0 PCI bridge: Texas Instruments XIO2001 PCI Express-to-PCI Bridge (prog-if 00 [Normal decode])
            Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
            Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
            Latency: 0, Cache Line Size: 4 bytes
            Bus: primary=02, secondary=03, subordinate=03, sec-latency=32
            I/O behind bridge: 0000d000-0000dfff
            Memory behind bridge: fc800000-fcffffff
            Prefetchable memory behind bridge: 00000000fd400000-00000000fd7fffff
            Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-
            BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                    PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
            Capabilities: [40] Subsystem: Gammagraphx, Inc. (or missing ID) Device 0000
            Capabilities: [48] Power Management version 3
                    Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                    Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
                    Bridge: PM- B3+
            Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+
                    Address: 0000000000000000  Data: 0000
            Capabilities: [70] Express (v2) PCI/PCI-X Bridge, MSI 00
                    DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
                            ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
                    DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry-
                            MaxPayload 128 bytes, MaxReadReq 512 bytes
                    DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
                    LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <16us
                            ClockPM+ Surprise- LLActRep- BwNot-
                    LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk+
                            ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                    LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
                    DevCap2: Completion Timeout: Not Supported, TimeoutDis-
                    DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
                    LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
                             Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                             Compliance De-emphasis: -6dB
                    LnkSta2: Current De-emphasis Level: -6dB
            Capabilities: [100 v1] Advanced Error Reporting
                    UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                    UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                    UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                    CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                    CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                    AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-

    03:00.0 Non-VGA unclassified device: Texas Instruments TMS320C6414 TMS320C6415 TMS320C6416 (rev 01)
            Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
            Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
            Latency: 32, Cache Line Size: 4 bytes
            Interrupt: pin A routed to IRQ 3
            Region 0: Memory at fd400000 (32-bit, prefetchable) [size=4M]
            Region 1: Memory at fc800000 (32-bit, non-prefetchable) [size=8M]
            Region 2: I/O ports at df00 [size=16]
            Capabilities: [40] Power Management version 2
                    Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                    Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

    Thank you.

  • 0 in reply to Yuan Gao1
    Guru 317370 points

    The cache line size is set to 4. (Why?)
    The TMS320C6205 Errata document says that it must be greater than 4, otherwise, memory read line commands (which are likely to be used for prefetching) will fail.

    There are a bunch of other possible PCI bus errors listed in that document.

    Furthermore, check that the memory range is correctly configured in the C6205.