Determining when to use SerDes

Anthony Campos

In reading the LVDS User's Manual it seems ideal to interface an FPGA with a SerDes and transmit data serially. What is the main driver in deciding to use this approach as opposed to transmitting let's say 10 individual status bits over 10 LVDS pairs, at DC to very low speeds? It seems the only advantage is cable weight, being that I would need to transmit over 5-10 meters.

over 13 years ago

0 Amritraj Khattoi over 13 years ago

TI__Prodigy 175 points

Hi Anthony

There are several advantages to using SerDes over parallel LVDS even at lower speeds. I am mentioning a few here.

1. Lower the number of layers on the PCB board.

2. Reduce the weight and cost of the cable used.

3. A higher speed balanced serial link generally has lower EMI emissions than a slower speed large bus.

Regards,

Raj

0 Anthony Campos over 13 years ago in reply to Amritraj Khattoi

Intellectual 400 points

Raj,

Can you elaborate on number 3? Why would a higher speed link have lower EMI emissions than slower speed large bus. Is this purely based on the FPGA's Simulataneous Switching Outputs?

0 Amritraj Khattoi over 13 years ago in reply to Anthony Campos

TI__Prodigy 175 points

Hi Anthony

There a a couple of reasons which lead to lower emissions in the serial domain.

1. The parallel domain has a lot of simultaneously switching outputs

2. Generally the serial stream is a low voltage signal as opposed to the parallel outputs which tend to be in the order of 1.8V to 3.3V.

Regards,

Raj

0 Avi Chami1 over 13 years ago in reply to Amritraj Khattoi

Mastermind 7395 points

I would add, on the advantages of the Serdes, that you don't have to worry about skew between the data and clock lines of the parallel LVDS solution.

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Determining when to use SerDes