I'm having an issue with an LVDS display "flickering" . The root cause has been determined to the RGB data bus, DE, and pixel clock from a processor having too much jitter.
The pixel clock appears to have up to 1.26ns of jitter (cycle to cycle). When triggering on the data/DE edges, the clock edge does not jitter, which leads me to believe that the enitre bus is jittering, not just the clock. The transmitter is a DS90C385 and the receiver is a EP102 (Tiawaneese component). When I change to the DS90CF386 on the LCD, the flickering issue appears to go away.
However, when doing calculations described in app. note AN-1059, the EP102 should have greater jitter tolerance than the DS90CF386. The specified receive bit position is 0.49/1.19ns (TI) and bit center +3ns (EP). I assumed the DS90CF386 to have the property of bit center +.35ns, as my frequency is 28MHz, not 85MHz.
Any idea why I see better performance with the receiver change? Why would the jitter tolerance appear to be better when the calculation shows it should be worse? Could this be a function of some PLL quality or some inner compensation for spread spectrum with the TI parts? Did I simply miscalculate?
