Hello,
I have some questions (Q1 to Q4) about TLK10002.
[Q1]
Are the following descriptions of datasheet mistakes?
<datasheet(SLLSE75) P69>
HS/LS Data Rate Setting (Refer to Table 4 for more CPRI/OBSAI Rates) – Write 4’b1101 to 2.3:0 HS_PLL_MULT[3:0], write 2’b00 to 3.9:8 HS_RATE_RX[1:0], write 2’b00 to 3.1:0 HS_RATE_TX[1:0], to select FULL rate and 20x MPY on HS side (HS_SERDES_CONTROL_1 = 0x811D, HS_SERDES_CONTROL_2 = 0xA444). – Write 4’b1001 to 6.3:0 LS_MPY[3:0], write 2’b00 to 7.9:8 LS_IN_RATE[1:0], write 2’b00 to 7.1:0 LS_OUT_RATE [1:0], to select FULL rate and 20x MPY on LS side (LS_SERDES_CONTROL_1 = 0xF119, LS_SERDES_CONTROL_2 = 0xDC04).
・Table 4 → Table 3 ?
・2’b00 to 3.9:8 HS_RATE_RX[1:0] → 2’b01 to 3.9:8 HS_RATE_RX[1:0] ?
・2’b00 to 3.1:0 HS_RATE_TX[1:0] → 2’b01 to 3.1:0 HS_RATE_TX[1:0] ?
・FULL → HALF ?
・0xA444 → 0xA545 ?
[Q2]
As for the following descriptions, which is right?
<datasheet(SLLSE75) P49>
・LATENCY_MEASURE_CONTROL Default:0x7F00 or 16.15:8 RESERVED for TI use only (Default 8'b11111111).
[Q3]
It is a question about registers setting. <datasheet(SLLSE75) P69>
May I set a register in order of an address number after Device Pin Settings?
for example, set 0x00 → set 0x01 → ・・・ → set 0x1F
[Q4]
Do you have the delay data from INx0P/N (HSRXxP/N) to HSTXxP/N (OUTx0P/N) by the following setting?
<Setting>
1:1 Mode, REFCLK frequency = 122.88MHz, Mode = Transceiver, 1 to 1 serialization on LS side inputs and 1 to 1 deserialization on HS side inputs.
Best regards,
H.Katsunaga
