• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 34 subscribers
  • Views 413 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TL16C754C DMA Understanding

1258021
Genius 5120 points

Other Parts Discussed in Thread: TL16C754C, OMAP-L138

Hi,

We are using TL16C754C. I read through the DMA Mode 1 operation.

So, Ideally when we configure our DMA controller the data need to be read as long as RXRDY signal is active low.

Please clarify.

We are using a TL16C754C package which doesn't contain these signals. So, I want to know if there are any registers which will tell about the number of bytes available in the FIFO?

Regards,

GSR

  • 0
    Prodigy 80 points

    Hi

    You can use the FIFORdy register to know the status of the RX fifo

    if this bit is active it can infer two possibilities

    1. The RX FIFO  has more bytes then FIFO threshold .

    2. Time out has occurred (the number of byte is less then  FIFO threshold)

    you can read the IIR register to verify if it is a time out condition (if yes you can not know what is the FIFO depth), if it is not a time out, you can read a burst of bytes( threshold size)

     please note: if the FIFO has entry which includes an error, the FIFORdy  bit will be set to low.

    In this case your host must handle the reading process (via error interrupt) until it removes  the error from the FIFO.

    Assaf

  • 0 in reply to Assaf Avram
    Genius 5120 points

    Hi Assaf,

    Thanks for the reply.

    I am looking at the timings of the TL16C754C.

    My understanding is the entire bus operation requires the following timing duration for UART.

    For write access:

    t6s + t13w + GRETAEROF (t6h, t16h). After write operation we need to provide 40nS delay.

    So in numbers we need to provide a total of 140nS timing cycle for write operation

    Similarly for read access:

    t6s + t7w + GRETAEROF (t6h, t12h). After write operation we need to provide 40nS delay.

    So in numbers we need to provide a total of (20 + 85 + 35)=140nS timing cycle for read operation.

    After one read operation we need to provide 85nS.

    Please let me know if my understanding is correct or wrong.

    Write know for write I have 80nS (For setup) + 160nS (For Strobe) + 80nS (Hold) + 120nS (Turn Around Time).

    I wish to optimize the timing parameters, if my above understanding is correct.

    Regards,

    GSR

  • 0 in reply to 1258021
    TI__Expert 5230 points

    Hi GSR,

    Your numbers for the write cycle and the read cycle are correct for 1.8V Vcc, however the write cycle delay (t15d) is 85 ns and not 40ns.

    Thank you.

    Best Regards,

    Joe

  • 0 in reply to Joe Fockler
    Genius 5120 points

    Hi Joe,

    Thanks for confirming the timing values.

    EMIFA controller present on (OMAp-L138) doesn't insert turn around cycles if current read operation was directly proceeded by another read operation.

    So I see two possibilities here

    1. Modify the driver so that after every read/write operation write/read operation proceeds
    2. Else include the turn around time cycles in strobe and hold time if it is acceptable for TL16C754C IC
    Or else can you suggest a better method for this?

    Regards,

    GSR