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TLK110 power up issue

Alex Marcoux
Intellectual 515 points
Other Parts Discussed in Thread: TLK110

Hi,

I'm helping a customer who as the following problem:

I am using the TLK110 Ethernet PHY with a single 3.3V supply. The 1.5V is generated by the TLK110. When I power-up my board with a bench power-supply, the TLK110 freezes. There is no data coming out of the MDIO pin so I cannot even read the PHY Idenfifier Registers. On power-up I hold the RESETN pin of the PHY low until the processor completes initialization (a few seconds). Toggling the RESETN line does not correct the situation. I have noticed that this happens only when the 3.3V rises slowly (50 ms). If I use a different power supply so that Vcc risese more quickly (1 ms) it does not happen. The rise time of the 3.3V should not make a difference since I hold the TLK110 in Reset until the voltage is stable at 3.3V. I have also noticed the when the TLK110 freezes, I can make it functional again by toggling manually the JTAG_TRSTN line. All JTAG pins are unconnected in this design (the JTAG input pins have internal pull-ups). Is this a known issue with the TLK110? Is there another workaround? Why does is seem to be stuck in JTAG mode.

Alex

  • 0
    TI__Guru 71526 points

    See datasheet section 3.2.2 concerning power supply sequencing with dual supplies.

    Also, what is the status of the SMI during the power-on and RESET?  See section 4.3 concerning static requirement of SMI after power-up and RESET.

    Section 6.1 defines the RESETN requirement.

    And 9.6.2 shows the XI Clock requirement during RESETN.

    If all these conditions are being met, we will need to see schematic and configuration information to analyze further.

    -Leonard

     

     

  • 0 in reply to LeonardEllis
    Prodigy 10 points

    Here are some answers to the items from the datasheet that you wanted verified:

    Section 3.2.2: This section does not apply to me since I am using a single supply.

    Power-on and RESET: No data is sent on the SMI during power-up and RESET.

    Section 6.1: The RESETN pulse lasts 650 us which is more than the required 1 us. We also wait more than the required 200 us after the Reset is released before we start communication on the SMI.

    Section 9.6.2: XI clock is present and stable during RESETN.

    I did more tests and found the following:

    1- The problem is not present on all of our prototypes. I can reproduce it on two out of 6 prototypes.

    2- When the TLK110 is frozen (no data coming out of the MDIO line so the PHY Identifier is read as FFFF FFFF), I had already noticed that toggling the JTAG_TRSTN pin unlocks it and allows me to read a valid PHY Identifier. I also noticed that pulsing the JTAG_CLK  pin also unlocks it.

    3- I disconnected the MDC and MDIO lines from from the TLK110 on my PCB and connected it to the TLK110 on the Eval board. I also connected Ground and 3.3V to power the Eval board. In this configuration I could not reproduce the problem. Then I swapped the TLK110 chips: I put the one from the Eval board on my PCB and the chip from my PCB on the eval board. After that I could not reproduce the problem on my prototype.Then I again disconnected the MDC and MDIO lines from the TLK110 on my board and connected it to the TLK110 on the Eval board. The Eval board now has the problem: the TLK110 is freezes on power-up and the JTAG Reset or Clock needs to be toggled to allow me to read the PHY Identifier registers.

    Why does the TLK110 get stuck in what seems related to the JTAG interface? There is nothing connected to the JTAG lines on my PCB.

  • 0 in reply to Sylvain Martel
    TI__Intellectual 1720 points

    Hi,

    We have noticed in some cases that long 3.3V rise might cause this behavior. It depends in the power up rise behavior and shape.

    The dependency on the MDIO/C or JTAG interface is not clear for us for the moment, can you please send us your schematics for review?

    In addition, sometime over-caps on board might casue this behavior, can you please send a scope capture of your power up rise time, how it looks? with the changes and ater the changes?

    Please send it us directly, we can assist you faster: <email address removed>

    Thanks & Regards,

    Oren

  • 0 in reply to Oren Shalita
    TI__Mastermind 31600 points

    I have moved this post to the Ethernet forum so that it can serve as a reference to others who might have similar questions.

    Patrick