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Latch timing of Bootstrap configuration pin value on TLK110

Daisuke Maeda
Guru 20205 points

Bootstrap configuration pin is described in "SLLS901A - 3.1 Bootstrap Configuration".

 "The logic states of these pins are sampled during reset..."

A hardware reset require a duration of at least 1us.

Is Bootstrap configuration pin value latched during this 1us?

Best regards,

Daisuke

 

  • 0
    TI__Intellectual 2000 points

    Hi,

    yes all the bootstrap configuration pins are latched to the PHY during reset (or during power up were there is internal power on reset of ~ 270ms). the 1us is a minimum requirement for the width of the hardware reset_n pulse. if some bootstrap configuration pins are not externally pulled up or down, then the internal (weak) PU PD will set the value to be latched.

    Regards,

    Aviad

     

  • 0 in reply to aviad
    Guru 20205 points

    Hi Aviad,

    Thank you for your reply.

    Is "internal power on reset of ~ 270ms" which you said 't1' in "9.6.1 Power Up Timing"?
    Is not there MAX of this 't1'?

    A hardware reset has a duration of internal reset.

     "The time from the point when the reset pin is de-asserted to the point when the reset has concluded internally is approximately 200us."

    When the RESETN pin is de-asserted, have all the bootstrap configuration pins already been latched?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Intellectual 2000 points

    Hi Daisuke,

    • you were right for pointing out "t1" in 9.6.1 power up timing" though we have a mistake in the data sheet and the units are ms and not μs in this specific table. this TYPO is corrected in the new revision of the data sheet which is about to publish. so it is indeed  power on reset of ~ 270ms. this internal POR function is enabled by default, as long as pin number 20 is either pulled up or left floating (weak internal pull up).
    • an external HW_RSTN does not necesarily have the duration of the internal POR. you can initiate an external HW_RESETN with a minimal pulse width of 1μs (after the power is ramped up). then you should wait for 200μs (the latching of the boot strap configurations + internal circuits to settle).

    Regards,

    Aviad

  • 0 in reply to aviad
    Guru 20205 points

    Hi Aviad,

    Thank you for your reply.

    For the latching of the boot strap configurations, I wait for at least 200μs after RESETN pin was de-asserted.

    There is the following comment in "6 Reset and Power Down Operation".

     "At power-up, if required by the system, the RESETN pin (active low) should be de-asserted 200μs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize."

    Is this "200μs" enough?
    Is the unit right?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Intellectual 2000 points

    Hi Daisuke,

    after the power has ramped,  the 200μs is enough and the unit :μs is correct.

    Thanks,

    Aviad

  • 0 in reply to aviad
    Guru 20205 points

    Hi Aviad,

    Thank you for your reply.

    All doubt was cleared.

    Best regards,

    Daisuke

     

  • 0 in reply to aviad
    Guru 20205 points

    Hi Aviad,

    There is a new question.

    For dual function pins become enabled as outputs, if the internal POR is not used and an external HW_RSTN is used, after the power is ramped up, is not a wait of ~ 270ms necessary?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Intellectual 2000 points

    Hello Daisuke,

    after the power has ramped up, if you apply external HW_RSTN  you need not wait more than 200us for PHY normal operation including the latching of the HW_configuration strapping pins. the ~270ms wake up time of internal POR was given to allow slow power supplies to ramp up before disengaging the reset on power up.

    Thanks,

    Aviad

      

  • 0 in reply to aviad
    Guru 20205 points

    Hi Aviad,

    Thank you for your reply.

    Best regards,

    Daisuke