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XIO1100 REFCLK Issue

Tom N
Intellectual 290 points
Other Parts Discussed in Thread: XIO1100

Hi,

I am trying to get the XIO1100 Phy to produce RX_DATA using external loopback wiring from the TXn/p port to the RXn/p port while supplying TX_DATA, TX_CLK, REFCLK, etc.  The issue that I am having is that I cannot get any data when I use the 125MHz single-ended clock for REFCLK+ as defined in the specification.  The 100MHz differential clock works fine, but the 125MHz single-ended clock isn't working.  I see no output from RX_CLK or RX_DATA.  Unfortunately, my end application requires the use of the 125MHz REFCLK.

I am setting the CLK_SEL pin high during reset and setting the REFCLK- pin to VSS as described in the specification.

Any ideas of what I may be doing wrong?

Regards,

Tom

  • 0
    TI__Guru* 76130 points

    Sorry for the delay,

    We are reviewing this and we'll reply soon.

    Regards.

  • 0 in reply to Elias Villegas M.
    Intellectual 290 points

    Thanks Elias. 

    We are seeing this behavior on two different XIO1100 devices.  We are using an automated test system to exercise the device, so if you have some ideas for us to try, we can modify our stimulus accordingly to see if the device responds. 

    We were able to get a valid output with a 100MHz differential clock.  We were also able to get an output, although with many errors, using a 125MHz differential clock.  But on both devices, the 125MHz single-ended clock produced no output.

    We need to get this resolved as soon as possible so we can continue to make progress with our application development.

    Regards,

    Tom

  • 0 in reply to Tom N
    TI__Guru* 76130 points

    Hello,

    The loopback operation should be very straight forward, are you actually achieving the loopback operation using the 100MHz clock?

    If so, the only think I can think of is that your 125MHz single ended clock is out of spec.

    Does the device works correctly with single ended 125MHz clock when you are not in loopback mode?

    How are you connecting the pin DDR_EN? If you change its connection do you see a different result?

    I will ask to another engineers for a possible known issue.

    Regards.

  • 0 in reply to Elias Villegas M.
    Intellectual 290 points

    Hi Elias,

    I think we found the issue yesterday, but we haven't validated it yet. 

    The REFCLK pin VIH isn't based on VDD_IO which is 1.5V.  The REFCLK is based on the 3.3V supply, so we need to modify VIH.  I'm pretty sure this will resolve the issue.  I will let you know if there is still a problem.

    Thanks again,

    Tom