TLK2541 jitter requirement

Hi Daniel,

The specified jitter does include both random and deterministic jitter. It is always best practice to try achieve as close to the listed spec's of the part as possible. At 90ps you are at almost double what the part is spec'ed for on the max jitter allowed.

Do you have the 8B/10B encoder enabled?

When the SYNCEN pin is held low the data does not byte align. You may be missing the start bit because your data is not aligned correctly.

Regards,

Mike

Hi  Mike

I have enabled 8B/10B encoder.

About jitter, I have attached the test report, I measured the clock at output of clock buffer, and the clock will send to TLK2541.

From the spec, the peak to peak jitter < 40ps. If so, I think the actual value should be 4.4230ps? But i am not sure the value is accurate.

Even we use current design, no package lost on TX, some package lost on RX, and it strange that it's normal on normal temperature. The issue will appear at 45C.

And maybe two days, no package lost and lost some package at the third day on RX.

Is it related with SYNCEN pin or jitter?

2806.mhtml_file___C__Users_dell_Desktop_6060_Clock_Jitter_Jitter_121.pdf

Thanks.

Hi Daniel,

The issue you are having is caused by jitter. If the SYNCEN was causing the issue I suspect that the IC would be giving you errors more than every three days. Try tightening up your jitter to meet the parts specs and rerun your tests.

Regards,

Mike