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DP83640 - How would one properly configure for IEEE1588 PTP-V1 Implementation? - Unable to insert timestamp into Tx Synce message

Neil Hindle
Prodigy 30 points
Other Parts Discussed in Thread: DP83640

I am trying to use the DP83640 chip to implement PTP-V1 in a FPGA embedded system architecture.

The issue encountered is that the DP83640 will not insert the transmit timestamp into the PTP sync message.  The issue most likely lies in the configuration of the DP chip.

The chip is configured as follows:

// Configure PHY Chip
emac32_write_md( pDev->pEmac32Drv, PHY_REG_PAGESEL, 0); // Page 0
emac32_write_md( pDev->pEmac32Drv, PHY_REG_PHYCR, 0x8041 ); // Enable Auto-MDIX. Set LEDs to mode 3. Set Phy Port to 1clkSrc

clkSrc = 0; // Use internal 125MHz clock with no division

clkSrcPeriodNanoSec = 0;

emac32_write_md( pDev->pEmac32Drv, PHY_REG_PAGESEL, 0x6); // Select Page 6
reg = (((uint16_t)clkSrc) << 14) | (uint16_t)clkSrcPeriodNanoSec;
emac32_write_md( pDev->pEmac32Drv, PHY_REG_PTP_CLKSRC, reg);

emac32_write_md( pDev->pEmac32Drv, PHY_REG_PAGESEL, 0x05);
emac32_write_md( pDev->pEmac32Drv, PHY_REG_PTP_TXCFG0, 0xAEE1); //Sync 1 step = 1, delay req insertion = 1, ignore 2 step = 1,  check one step  = 1, crc correction = 1,

emac32_write_md( pDev->pEmac32Drv, PHY_REG_PTP_RXCFG0, 0x01E1 );  //ip domain 224.0.1.129

emac32_write_md( pDev->pEmac32Drv, PHY_REG_PTP_RXCFG3, 0x0D00 );  // PTP Rx Configuration Register 3: Set Rx timestamp insertion (bit 8) and keep TS on error

emac32_write_md( pDev->pEmac32Drv, PHY_REG_PTP_RXCFG4, 0x7B28 );  // timestamp seconds insert offset 40, nanoseconds offset 44

Thanks for your time all recommendations welcome.

--N

  • 0
    TI__Mastermind 31600 points

    Neil,

    Have you reviewed the Software Development Guide (SDG) and the EPL C code reference library?  These include implementation details beyond what is in the datasheet.  The SDG and EPL are available on-line at:

    http://www.ti.com/tool/dp83640sw-lib

    If so and you are still seeing the problem, we will need to review the device configuration and the packet contents to make sure they are aligned.  For the register dump, we will need to see all register addresses on all register pages.  For the packet contents, you can capture the packets using your software or using a network utility like Wireshark. 

    Patrick

     

  • 0 in reply to Patrick OFarrell
    Prodigy 100 points

    Patrick,

    I too am facing a similar problem.The issue is that i have configured it as two-step clock and i am unable to Tx timestamp

    of sync message.I have used EPL C code reference library.

    The chip is configured as follows:

    // Enable Transmit Timestamp operation
        flags = TXOPT_IP1588_EN | TXOPT_IPV4_EN | TXOPT_TS_EN;

    PTPSetTransmitConfig( portHandle, flags, 1, 0xFF, 0x00);

    //Every 50ms polling PHY_PG4_PTP_STS to check if there are any events:

    if(i_timer_msec%50 == 0)
    {
            events = PTPCheckForEvents( portHandle);
            if ( events & PTPEVT_EVENT_TIMESTAMP_BIT)
            {
                   PTPGetEvent( portHandle, &eventNum, &riseFlag, &seconds_ts, &nanoseconds_ts, &eventsMissed);
            }
            if ( events & PTPEVT_TRANSMIT_TIMESTAMP_BIT)
            {
                   PTPGetTransmitTimestamp( portHandle, &seconds_ts_sync, &nanoseconds_ts_sync, &overflowCount);
            }
    }

    I have attached a wireshark file, please take look at PTP packets.


    Hi Neil,
    Is the issue resolved in your design. Could you please make some suggestions.


    Regards,
    Swathi

  • 0 in reply to swathi murali
    Prodigy 30 points

    The one step PTP operation of inserting the timestamp into the Sync message at hardware level still is not working.  Due to implementation a stop gap of manually inserting the timestamp into the sync message has been suffice so far.  

    Two step implementation sends the transmit time in a follow up message where the timestamp is taken from the phy chip.  I have not done two-step as I needed 1-step implementation.