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DP83640 ethernet Frame Length

Hemant Ghayal
Intellectual 265 points
Other Parts Discussed in Thread: DP83640, DP83630

I have a special application in which I intend to use the DP83640 in 100BaseFX mode, and should have etherent frames of arbitrarily long length. In fact I do not want to close the MII frame once opened with TX_EN assertion at all. Will the corresponding MII on the remote end pass on valid data to its MAC? My intention is to superimpose my own TDM frame structure over the MAC frame, which I want to go on continuously. In short I want to use the device as a serializer of MAC data after opening the MAC frame once using TX_EN. 

Will the DP83640 allow such infinite frame operation?

  • 0
    Intellectual 265 points

    I add to the above discussion, I would also like to know whether the Phy needs any minimum number of IDLE codes to declare the link to be up. One of  Intel Phys LXT973 needs minimum 12 IDLS codes every 2 ms for the link to be declared up, which in turn will determine how long an ethernet frame can continue before which it has to close by de-asserting TX_EN so that required number of IDLE codes are sent, before a new frame starts. Does this restriction apply to DP83640 also? If yes, can this feature be disabled? And if it can be disabled, will it allow bigger size (or infinite length) ethernet frames on DP83640? Can we say the same thing about other 10/100 Phy from TI/National also, such as  DP83630 and DP83849?

  • 0 in reply to Hemant Ghayal
    TI__Intellectual 1225 points

    Hi Hemant Ghayal,

       When SD_OPTION set to 0, Link will be maintained as long as signal level is valid and Descrambler remains locked,  you can see the SD_OPTION funtion on page 61 of the datasheet.  But please be carefull the Threshold violation function.

       We aslo have DESC_TIME function, but I think it is not helpfull, this only allow reception of packets up to 9kB in size.

       For other DP83** products, you can confirm your function for DP8340 then compare with the datasheet.

       Hope for catch your mind.

     

    Mister Lei

    11/14/2012

  • 0 in reply to Mister Lei
    Intellectual 265 points

    Hi Lei,

    Would you like to answer my question again considering  that we intend to use the ICs only for 100BaseFX operation, and hence the scrambler/descrambler functions would be bypassed? In such case under what circumstances the link is likely to be declared lost if the other end activates TX_EN permanently, and the signal path (i.e. Fiber) is not broken?

    With Regards

    Hemant

  • 0 in reply to Hemant Ghayal
    TI__Mastermind 31600 points

    Hemant,

    What will the overall system look like?  Will it include a DP83640 on both ends of the link? Will both sides of the link be transmitting continuously (without any idles between data)?

    What interface will be used for the connection between the DP83640 and the MAC?  Will it be MII or RMII?

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 265 points

    Hi Patrick,

    The system will have DP83640 on both sides. The interface for the user will be MII, as RMII needs periodic correction due to clock rate mismatch between local clock and recovered clock, and which cannot be permitted in our aplication through frame closing.

    The intention is to open a frame by asserting TX-EN and then continue to transmit without closing the frame through deactivation of TX_EN. Hence there may not be any 5-bit IDLE codes sent at all.  Only in exceptional cases, as a part of error recovery, the TX_EN will be desserted and asserted again. Otherwise the intendeed use is to send an infinite length ethernet frame. The application is to use the phy  as a 4-bit serdes after asserting TX_EN.

    As already mentioned we will use fiber as medium. Hence scrambler/descrambler will be bypassed, I guess.

    Regards,

     

    Ghayal