In section 11.1 (Operating, Timing, and Switching Characteristics of XI) datasheet specifies voltage levels of XI to be minimum 0.63*Vdda_33 (Vdda_33 is 3.3V!)
In table 2-8 (Clock terminals) It is said: XI is a 1.8-V CMOS input. Oscillator jitter must be 5-ps RMS or better. If only 3.3-V oscillators can be acquired, great care must be taken to not introduce significant jitter by the means used to level shift from 3.3 V to 1.8 V.
To me it is contradictory. Which one is good? I saw that the eval board schematics uses a 3.3V oscillator with resistor dividers. If it is a 1.8V input, then the electrical specifications has to be updated and not related to Vdda_33 which is 3.3V.
Thaks a lot!
