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DP83620 CLK_OUT

Matteo Vit1
Prodigy 20 points
Other Parts Discussed in Thread: DP83620

Hello,

I'm using the DP83620 PHY in RMII Master mode (RX_DV and TXD_3 are strapped high). The input clock is 25MHz. The RMII Master mode is confirmed by the value of the RMII and Bypass Register (RBR) 0x17 which has value 0x4021. The output from RX_CLK and TX_CLK is 50MHz as expected, while the output from CLK_OUT is 25MHz. I was expecting 50MHz too. Has anybody tried this configuration?

Regards,

Matteo

  • 0
    TI__Mastermind 31600 points

    Matteo,

    I believe you have identified a gap in the documentation.  Could you please perform the following register configuration to see if this resolves your question?

    1. Write register address 0x13 to 0x0006.
    2. Read register address 0x14.  The expected value should be 0x800A
    3. Write register address 0x14 to 0x000A.
    4. Write register address 0x13 to 0x0000.

    At this point, I believe that CLK_OUT should be 50MHz.  Could you please confirm?

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 20 points

    Hi Patrick,

    I tried your write sequence and it works. I can see the 50MHz clock on CLK_OUT.

    Thank you,

    Matteo