SN65LV1224B does not lock

Hi Wolfgang,

In the case when the receiver is not locking, what is changing? Is your Ref clock stable? Also, what does your pattern look like? In the case where there is a consecutive one zero pattern the device may take longer to lock because it is looking for a a start bit. You can try extending your time out to see if that changes anything.

Regards,

Mike

Dear Mike,

at the moment we think the behaviour could come from too much clock input jitter on the serializer or the refclk jitter on the de-serializer or both together. We have PLLs on each side to generate the clock signal and we see different slight different behaviour if we change the PLL settings with the same clock. We could lower the jitter from 250ps to 150ps with different PLL settings and a different oscillator, but it did not disappeared. I will measure the receiver side later on.

The timeout is some seconds and we did not see the LOCK coming after some time, if it is not locking.

How will the serializer and de-serializer behave if the jitter is to high?

Best regards,

Wolfgang

Hi Wolfgang,

250ps of jitter is outside the spec of the part so I cannot confidently tell you how the part will behave in a situation like that. Try to operate the part in its recommended operating region and and see if you receive better results. Please follow back up with me so we can try to solve this issue. I look forward to hearing from you soon.

Regards,

Mike

Dear Mike,

I have checked the input clocks on both side and both look fine now. Still we see that the receiver does not lock with a static input pattern like 0000000001b and no sync pattern. Is this a known behaviour?

regards,

Wolfgang

Hi Wolfgang,

I am going to take an EVM into the lab today and try to duplicate your problem. Can you provide me with the specifics of your setup so that I can best match them in my lab?

V_CC, Data Pattern, Input Frequency, Jitter, ect.

Regards,

Mike

Hi Wolfgang,

In order for the SN65LV1224B to lock one of two things has to happen.

1. The synch pin on the SN65LV1023A needs to be toggled forcing the serializer to send 111111000000, allowing for only ONE 10 transition within the first twelve bit frame.
2. The input/start-up pattern needs to avoid having a 01 transition to start with because the SN65LB1224B is looking for 10 to lock. It will see 1010 and sit idle not knowing what pattern to lock to.  

So you need to either toggle that synch pin or adjust your input pattern. Let me know how it turns out.

Regards,

Mike

Dear Mike,

here is our setup:

Transmitter SN65LV1023A

SYNC1,2 = 0V

DVCC, AVCC, TCLK_RF, PWRDN, DEN = 3,3V

TCLK = 30Mhz

DIN0-9 = 0111110001

Receiver SN65LV1224B

DVCC, AVCC, PWRDN, REB, RCLK_RF = 3,3V

REFCLK = 30Mhz

LVDS transmit pattern (it seems that the transmitter works correct):

8468.LVDS Pattern small.tif

So we have 2 0-1 transitions in our data. I was aware that this could lead to a false lock as this is mentioned in the datasheet.

But that the receiver could not lock at all is new for me and not noted in the datasheet.

best regards,

Wolfgang