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HD-SDI clock issue

Katrina Barnes
Prodigy 20 points
Other Parts Discussed in Thread: LMH0340, LMH0341

I am currently working with a board that uses the LMH0340/0341 serdes pair.  I am try to perform a BERT by outputting a counter from an FPGA, out to a serializer (LMH0340), loop through to the input of the board, through a deserializer (LMH0341) and into another FPGA on the board.  The serializer locks onto output clock from the first FPGA, but the deserializer seems to intermittently lock onto the transmitted clock.  Does anyone have an idea as to why this might be?  Thanks in advance.

  • 0
    Prodigy 20 points

    Is it possible that the deserializer loses its lock because the input data bits are not flipping frequently enough?  It is a 20 bit counter coming in, so there are times that there are 20 1's or 20 0's coming in.

  • 0 in reply to Katrina Barnes
    TI__Genius 13475 points

    Katrina

    There are a couple of possibilities - you could check your theory on the low transition density by scrambling the bits from your counter, or testing it with a smaller (5-bit?) counter.   If that is the issue, and your real data is liable to be also poorly behaved, then I would suggest a scrambling polynomial such as is used in the intended (broadcast video) application.

    Another possibility is that there is significant jitter on your clock driving the serializer.  If this is the case, then you should see the serializer loosing lock as well.

    Mark Sauerwald