I'm trying to use the PRBS and high/low/mixed frequency verification features on the TLK3134 to perform BER testing on my system. I have a verified operating hardware platform that is able to successfully receive multi-gigabit 8B10B signals from our source (a custom IC) using the TLK3134. The custom IC implements test modes that allow system 8B10B data to be replaced with test waveform outputs that should be compatible with the TLK3134 verification features. We'd like to use the verification features on the 3134 to run long duration BER tests to help quantify the error rates of the system.
I've enabled the PRBS waveform output on our device, and enabled the 3134 PRBS verification logic per the notes in the 3134 datasheet (section 3.4, "PRBS Test Generation and Verification Procedures"). When I read register 29 the first time, I see the expected 0xFFFD default value. Subsequent reads show 0xFFFF, as if the verifier is seeing errors and constantly saturating. I believe I have the registers set according to section 3.4, and have performed the datapath reset that's included in the sequence.
Does the verifier work if the chip is not being used with a loopback cable (i.e. if the source of the PRBS signal is something other than the 3134 transmitter)? Is there any documentation on the exact bit sequence the verifier is expecting ("PRBS7" is specified, but a document showing the exact bit sequence required would be good so that I can verify the sequence our device produces). Are there any other registers that need to be set up that aren't documented in the section 3.4 discussion? Does the verifier attempt to sync up with the incoming signal by performing a bit crawl or search on the incoming stream? If not, is there some requirement to sync the verifier with the source signal?
Also, I've attempted to use the low-frequency pattern verifier by setting register 16 bits 3..0 to 1001 binary, enabling the low-frequency pattern output on my test device, and checking register 21. In this case, register 21 remains 0, apparently indicating that the 3134 is not synchronized to the input test pattern. Reading error count register 22 gives a constant 0xFFFD value (the default never changes). Is there a requirement to sync the low frequency signal to the verifier, or is this automatic?
Any additional documentation on the verification features would be appreciated.
