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DP83640 GPIO3

Gunter H
Prodigy 200 points
Other Parts Discussed in Thread: DP83640

Hello,

When we reset the DP83640 with GPIO3 pulled high, we observe that it uses 75mW (give or take) more power than if GPIO3 is pulled low.

Is there an explanation?

Thanks!

Gunter

 

 

  • 0
    TI__Intellectual 1885 points

    Hello Gunter,

    What value resistor are you using to pull GPIO 3 high?

    What value resistor are you using to pull GPIO 3 low?

    Are you using your own design or are you using a TI DP83640 EVM?

    Thanks,

    John

  • 0 in reply to John Hamilton1
    TI__Intellectual 1885 points

    Hello Gunter,

    I confirmed on the bench that the DP83640 will draw about 25mA more current when GPIO3 is pulled high.

    GPIO3 is not a strap pin.

    Strapping or pulling GPIO3 High forces the DP83640 into a mode that the device is not intended to operate.

    You should avoid strapping this pin.

    Thanks,

    John

     

  • 0 in reply to John Hamilton1
    Prodigy 200 points

    Hi John, thanks for your help.

    Sorry I was sidetracked for a day with another issue and didn't answer your original question.

    We have this pin connected to an FPGA (for potential future use) and it is the FPGAs internal pull-ups during/before programming that is causing the issue.

    So ... we need to disconnect this pin from the FPGA as we don't have a means to independently rest the PHY after the FPGA is programmed.

    Thanks for your help,

    Gunter