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Chaining DP83620 based links with a master clock

Hemant Ghayal
Intellectual 265 points

Other Parts Discussed in Thread: DP83620, DP83630

Hello Patrick,

I have created a new post.

I was going through the DP83620 data sheet and found it useful that I can operate it in slave mode. Now is it possible to take the MII RX clock of the chip and distribute it over another  (downstream) ethernet link by using it as transmit clock of the  DP83620 connected to that link? In other words can the DP83620 transmit of a downstream link be synchronized to an external clock which is the recovered clock (RX CLOCK) of the previous stage? If yes, does it have to be dejittered before being used as a stable clock for the downstream stage? The purpose is to form a chain of ethernet links with a common clock which flows from upstream to downstream. Can this be achieved using DP83620? I see that the transmit clock of DP83620 is always slaved to the external clock source. So unless I source the external clock from previous stage, I cannot synchronize successive stages to a common master clock. Our applcation requires this sort of operation where we have a ring of nodes connected using ethernet links. And these links have to synchronize to the stable crystal clock of one of  the nodes, called the master node.

If this is not possible using DP83620 can you suggest an alternative? Of course we would prefer DP83620 for its costs and simplicity.

Regards,

Hemant Ghayal

 

  • 0
    TI__Mastermind 31600 points

    The DP83620 has multiple clock pins with different functions.  Based on the text of your post, I am unclear on your expectations so I would like to clarify the different clock pins to help make sure we are aligned.

    • TX_CLK:  MII transmit clock for data from the MAC
    • RX_CLK:  MII receive clock for data to the MAC
    • X1:  Crystal / oscillator input, the primary clock reference input for the device
    • CLK_OUT:  Configurable clock out that can provide

    When a DP83620 is configured for Synchronous Ethernet mode, the CLK_OUT pin can be configured to output a clock that is recovered from the 100M received data.  This clock should be synchronous to the (upstream) transmit clock of the link partner.  This clock can then be provided to the X1 input of a second DP83620 as shown in figure 5 of the Synchronous Ethernet application note, AN-1730 / Literature Number SNLA100 (http://www.ti.com/litv/pdf/snla100).  Is this the topology you are considering?

    Patrick

     

  • 0 in reply to Patrick OFarrell
    Intellectual 265 points

    Hi Patick,

    I do mean the same type of usage as shown in fig 5 of SNLA100. But I would like to go one step beyond and say that I want to have success stages of chained DP83620 devices such that the crystal clock of the first stage (I call it master clock) continues to propage downstream through Synchronous mode, nd using RX_CLK as X1 of next phy at every stage.  But in such case will the accumulated jitter become excessive unless I dejitter the CLK_OUT before giving it to X1 of the next Phy? How many stages can I have without de-jittering CLK_OUT? And do I need to de-jitter it at every stage?

    Hemant

  • 0 in reply to Hemant Ghayal
    TI__Mastermind 31600 points

    Hemant,

    I believe this topic was covered and resolved in the corresponding post at:

    http://e2e.ti.com/support/interface/industrial_interface/f/142/p/237019/856525.aspx

    In summary, if it is necessary to propagate the clock downstream, you will need to de-jitter it.  Please let me know if there is any additional detail specific to this post required to close this out. 

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 265 points

    Patrick,

    We can take the issue as resolved. You may want to suggest couple fo IC solution for de-jittering the 25 MHz clock?

    Presently we plan to try out the single clock MII mode of DP83630/DP83620 which allows pseudo-synchronization at individual nodes. We may look into synchronization across the nodes subsequently and will use your suggestions then.

    Regards,