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XPS_ETHERNETLITE + DP83640 PHY doesn't run (FMC-ISMNET)

Ravil Latipov
Prodigy 30 points
Other Parts Discussed in Thread: DP83640

Hi, this is post to Avnet tech support. It requires expertise on DP83640 vs DP83848 PHYs, so i post it here as well:

I have problem making standard design for Avnet LX16 board with XPS_ETHERNETLITE core working with FMC-ISMNET card (DP83640 PHY). This problem can be characterized as "XPS_ETHERNETLITE core in PLB design and DP83640 PHY don't work together". XPS version is 13.1. ISMNET card has two DP83640 PHYs, Avnet LX16 board has one DP83848 PHY. on-board DP83848 works fine with standard network designs for LX16 kit and also passes MII loopback test ("ls_emaclite_test_1" procedure, line 415 of \sys_test_0\src\ls_xemac_test.c file attached).

For ISMNET's DP83640 PHY fails MII loopback test with XPS_ETHERNETLITE core design. MDIO access to DP83640 works fine. All registers are readable and MII loopback mode sets fine. MII loopback test (in ls_emaclite_test_1) uses polling mode. it sends frame fine, but zero characters are received. In addition, I have a custom board with XC6SLX45 device and dual DP83640 PHYs, made with same schematic as ISMNET FMC card.

 XPS_ETHERNETLITE PLB design doesn't on that board either. Custom board has better access to pins, i probed it. Clocks and timing looks fine, except that for MII loopback PHY asserts RX_ER high for about 7 microseconds, so likely frame is discarded by MAC core. I haven't tried detailed Chipscope tests. It is not clear why DP83640 fails with XPS_ETHERNETLITE while DP83848 works fine.

 Please see source code, UCF/MHS files and log files with PHYs register maps in attached ZIP file.  C source code is derived from Avnet's and Xilinx examples and designs, there is nothing proprietary in it, please feel free to use it.

 ISMNET FMC doesn't come with either XPS_ETHERNETLITE or XPS LL TEMAC designs, only with custom IP core industrial Ethernet designs for LX150T kit.

 I think it would make sense to have XPS_ETHERNETLITE design running for ISMNET FMC either on LX16, SP605 or LX150T kit. I have SP605, ML605, LX16, ISMNET FMC kits in the lab (all except LX150T kit). i am almost sure that tracking this problem on either Spartan-6 kit and either PLB or AXI design will fix it.

 Thank you.

 

dp83640_xps_ethernetlite.zip
  • 0
    TI__Mastermind 31600 points

    Ravil,

    I would expect both the DP83640 and the DP83848 to pass MII loopback tests without any issues.  The issue you are seeing is not expected.

    I have a couple questions to help me understand the test scenario a bit better:

    • Once loopback is configured, a test frame is transmitted by the FPGA, correct? 
    • Does the problem occur for both DP83640 devices on the ISMNET card? 

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 30 points

    Patrick,

    yes, it is correct, once loopback is configured, test frame is transmitted by FPGA. Problem occurs with both

    devices on ISMNET card. ISMNET is FMC card, so it can be connected to pretty much any FPGA kit with

    FMC LPC (low pin count) connector. AVNET has reference designs for this card for LX150T kit. I also

    tested it with SP605 kit and it worked. It doesn't work with Avnet S6LX16 kit and custom board i have

    with XC6SLX45 device. Also it was reported not working with Zynq702 board. I understand that problem

    is timing margins for FPGA to PHY interface (likely RX) that occurs when XILINX tools synthesize for different

    pins on different FPGA packages. It is usually case for GMII and RGMII interfaces, where timing is more

    critical, but i didn't read about any issues with MII  interface timing problems. Pin strapping shouldn't

    be a factor. Registers state is good in all cases, test sets 100 mbit full duplex mode and loopback,

    it should be plug and play on all FPGA boards.  without loopback set, I am able to send packets to PC

    on TX interface. from about 16k packets about 1-2k first packets are lost, rest is transmitted. so i think that

    problem is with RX interface. more details are on Avnet forum, link: http://community.em.avnet.com/t5/FMC-ISMNET/XPS-ETHERNETLITE-DP83640-PHY-doesn-t-run-FMC-ISMNET/td-p/5810

    Avnet support didn't resolve it so far. Thank you.

     

  • 0 in reply to Ravil Latipov
    Prodigy 30 points

    It appears to be FPGA XST synthesis problem. I inserted Chipscope ILA core into design for XC6SLX45

    with dual DP83640 design. This changed layout inside of FPGA and now MII loopback works. So it is

    not PHY, but rather FPGA internal problem with this IP core. I guess one more argument of SOCs

    vs FPGA for embedded design. I should probably had used OMAP SOC (L-138, f.e.) interfaced with

    smaller FPGA  rather than dealing with FPGA embedded design issues. So it is not DP83640 PHY

    issue. Thanks.