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Display bringup - SN65DSI85 + Chimei N101JSF WUXGA pannel (1920 x 1200)

ABN BN
Prodigy 10 points
Other Parts Discussed in Thread: SN65DSI85

Hi All,

 

  I am working on  display bringup activity writing a driver for TI SN65DSI85 ( DSI BRIDGE TO FLATLINK LVDS) bridge + Chimei N101JSF WUXGA pannel (1920 x 1200). Driver development is done and able to genarate the test pattern on the pannel, but android boot up is not seen on the pannel (nothing is displayed only back light is on). In the interrupt status register  of SN65DSI85 observe the SOT error bit is set. Any suggestion how to debug this issue or slove this?

Thanks in advance, Any help would be greatly help us to proceed further.

 

Current configuration of SN65DSI85 is below

   1)Single channel DSI is used with 4 data lanes. DSI clock running at 840Mhz

   2)Channel A and B of LVDS is used together for oupting odd and even pixel. LVDS clock running at 79Mhz. 24bpp format

 

Below are the CSR register value updated in the SN65DSI85 via I2C interace during initalization

Register address : value      

0x00-0x08: [0x35],[0x38],[0x49],[0x53],[0x44],[0x20],[0x20],[0x20],[0x01] (Device ID )

0x0a: [0x85]

0x0b: [0x20]

0x0d: [0x01]

0x10: [0x26]

0x11: [0x00]

0x12: [0x50]

0x13: [0x00]

0x18: [0x6f]

0x19: [0x05]

0x1a: [0x00]

0x1b: [0x00]

0x20: [0x58]

0x21: [0x02]

0x22: [0x00]

0x23: [0x00]

0x24: [0x80]

0x25: [0x07]

0x26: [0x00]

0x27: [0x00]

0x28: [0x20]

0x29: [0x00]

0x2a: [0x00]

0x2b: [0x00]

0x2c: [0x20]

0x2d: [0x00]

0x2e: [0x00]

0x2f: [0x00]

0x30: [0x06]

0x31: [0x00]

0x32: [0x00]

0x33: [0x00]

0x34: [0x30]

0x35: [0x00]

0x36: [0x03]

0x37: [0x00]

0x38: [0x50]

0x39: [0x00]

0x3a: [0x11]

0x3b: [0x00]

0x3c: [0x00]

0x3d: [0x00]

0x3e: [0x00]

0xe0: [0x01] 0xe1: [0xfd] 0xe2: [0xfc] 0xe3: [0x00] 0xe4: [0x00] 0xe5: [0x0d] 0xe6: [0x00]

 

 With Regards,

ABN

  • 0
    Prodigy 180 points

    ABN,

    you have not identified the SoC you are using for this project. often the issue with the android builds for common SoC's is that the accelerated graphics drivers may not be properly loaded. if you are able to generate test patterns with a stock kernel and framebuffer, this would point to the android graphics libraries. without a full boot log and android startup log, it will be difficult to respond. please let us know what SoC you are using, what kernel version, if you have done pattern tests with standard framebuffer, what android build you are using, a bootlog, and android startup log.

  • 0
    TI__Intellectual 1990 points

    The max DSI CLK rate supported by this device is 500M which would provide 1Gbps/lane throughput.  840M exceeds the max supported CLK rate.  Are you referring to 420M CLK rate for 840Mbps throughput per lane?

    For the test pattern generation, are you using your host processor to generate the pattern or are you referring to the device generated test pattern?  If the device test pattern generation is to be used, you would have to enable the mode by setting 0x3C=0x10.  The register config above does not have this bit set.

    When the video stream starts before the device is configured(or any activity on the DSI interface), it can cause some of the error status bits to be set.  It is strongly recommended to follow the recommended initalization sequence as described in the datasheet(Recommended initialization Sequence section of the datasheet).  You should write all Fs to the corresponding error status bits to clear and read the latest status.

    The current configuration(per the register config provided above) enables IRQ.  I am afraid this may cause false interrupts that could cause initialzation issues you are running into when the device is not configured correctly.  Please have 0xE0, 0xE1 and 0xE2 set to all 0s and see if the bring-up issue goes away.

    I can provided recommended CFR setup once you confirm the questions addressed above.