SN65LVCP114 ORCAD Library

Hi,

I am tracking down the EVM files and I will share them with you when I find them.

Regards,

Mike

Hi,

Here are the schematic and footprint files for the SN65LVCP114.

5383.LVCP114_Lib.zip

Regards,

Mike

Thanks Mike.

Your attached file was very useful to me and my customer.

I have one question. Could you explain the function of AGC (Automatic Gain Control) of SN65LVCP114?

Hi JD,

When AGC is enabled the gain of the device will not drift over voltage and temperature (the gain is regulated).

Regards,

Mike

Hi Mike...

I need your help for SN65LVCP114.

My customer asked me what is the meaning of  'Peaking in dB when setting EQ.".

Fig.15 in the datasheet is typical EQ gain profile curve. 

Is X-axis a frequency and Y-axis a voltage?

Hi Avraka,

Peaking in dB is simply stating the max level of gain you can receive for each EQ setting on the SN65LVCP114. There is a typo in the data sheet on pages 5 & 6 in the table that explains the EQ settings. The right most column of the table in the GPIO mode box should read EQ[x]1 not EQ[x]0 so be aware of that while reviewing the EQ settings. To further elaborate on the peaking question, if we set EQ[x]1 and EQ[x]0 to a 1 or high state the maximum expected gain for that setting would be 13.9dB.

In Figure 15 of the data sheet the x-axis represents frequency and the y-axis represents gain for the different EQ settings, not voltage. If you have a channel where you expect to have a loss of approximately 14 dB you would use the aforementioned EQ setting of 13.9 dB and the SN65LVCP114 would provide you with enough gain to generate a flat response at 10GHz.

Regards,

Mike

Hi Avraka,

LPA is the enable pin for loopback mode on channel A of the device. Figure 13 in the data sheet shows an example of this.

Regards,

Mike