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PCI board based on Altera Acex not work in XIO2001EVM in GA-Z68X-UD7-B3 and GA-P41T-D3P

Alexander Virchenko
Prodigy 30 points
Other Parts Discussed in Thread: XIO2001EVM, XIO2001

Lately we have seen issues when trying to run the Altera Acex PCI board in XIO2001EVM on GA-Z68X-UD7-B3 and GA-P41T-D3P motherboards. Altera Acex PCI board is detected and enumerated, but our Windows driver fails (system freeze) when trying to read certain registers (tested in Windows 7 SP1 x64 and XPSP3 x86). On GA-B75-D3V, M2A-VM, P8H61-V, P5LD2 motherboards Altera Acex PCI board in XIO2001EVM work fine. Altera Acex PCI work fine in PCI slots on all tested motherboards (include  GA-Z68X-UD7-B3 and GA-P41T-D3P).

Thanks.

Alexander.

  • 0
    TI__Guru* 76130 points

    We are reviewing your question and we'll reply soon.

    Regards.

  • 0
    TI__Guru* 76130 points

    Hello,

    Sorry for the delay.

    You say the FPGA is enumerated but when reading some registers the PC freezes, are those Registers always the same ones which causes the failure? Can you access other different registers?

    Can you successfully establish a data communication with the FPGA?

    Does the failure occurs on different systems/PCs ?

    Are you able to take some Register Dumps for a failing case and for a passing case?

    Below are some items worth to check:

    The XIO2001 can only pass I/O adress above 0x100 as the bottom 12 bits of the I/O address base register are hardwired to 00. If a legacy device does not support 16 or 32 bit I/O addressing it will not work behind the XIO2001.

    Subtractive decode is not supported.

    The maximum payload size for a TLP is 512 Bytes.

    Check that the N_FTS_ASYNC_CLK and N_FTS_COMMON_CLK values in the Control and Diagnostic Register 2 are set to the correct value. I have seen ASPM fail if these values were incorrectly set to 0. I recommend that you use the default values specified in the datasheet. 

  • 0 in reply to Elias Villegas M.
    Prodigy 30 points

    Hello!

    "The XIO2001 can only pass I/O adress above 0x100 as the bottom 12 bits of the I/O address base register are hardwired to 00. If a legacy device does not support 16 or 32 bit I/O addressing it will not work behind the XIO2001......"

    It is a question ONLY of address space I/O, or it is applicable to address space of memory?
    This chip superimposes what limitations on entities in address space of memory?

    Kind regards

  • 0 in reply to Alexander Virchenko
    Prodigy 30 points

    Can you successfully establish a data communication with the FPGA?

    Only on some computers.

    "Does the failure occurs on different systems/PCs ?"

    The system completely freeze.

    "Are you able to take some Register Dumps for a failing case and for a passing case?"

    No. Because  the system completely freeze


    "Below are some items worth to check:

    The XIO2001 can only pass I/O adress above 0x100 as the bottom 12 bits of the I/O address base register are hardwired to 00. If a legacy device does not support 16 or 32 bit I/O addressing it will not work behind the XIO2001."

    It is a question ONLY of address space I/O, or it is applicable to address space of memory?
    This chip superimposes what limitations on entities in address space of memory?

    "Subtractive decode is not supported."

    We do not use

    "The maximum payload size for a TLP is 512 Bytes."

    We have less.


    Check that the N_FTS_ASYNC_CLK and N_FTS_COMMON_CLK values in the Control and Diagnostic Register 2 are set to the correct value. I have seen ASPM fail if these values were incorrectly set to 0. I recommend that you use the default values specified in the datasheet. 

  • 0 in reply to Alexander Virchenko
    TI__Guru* 76130 points

    Hello Alexander,

    Sorry I missed this thread. are you still having problems?

    Do you have more information or have you made further tests here?

    Regards.