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XIO2001

Jeff Brown
Prodigy 55 points
Other Parts Discussed in Thread: XIO2001

In the XIO2001 datasheet (SCPS212F Rev May 2012) it says to route the PCI clock being fed back to the XIO2001 (CLKOUT6 to CLK) 2.5 inches longer than the other device clocks (which probably delays it about 0.3 nsec) – which is a lot of extra routing.    We have one PCI device (in an FPGA) that is only about 0.25 inches away and I’m worried about skewing the clocks this much.  So, if we do not include this additional 2.5 inches (approx. 0.3 nsec) of clock skew can we simply offset the timings in Section 7.9 (which may not meet the PCI standards but as long as we can meet the new timings in our FPGA it shouldn’t matter)?

 

  • 0
    TI__Guru* 76130 points

    Hello Jeff,

    I can't find where it says that CLKOUT6 should be 2.5 inches longer.

    The requirement is that the feedback trace from CLKOUT6 to CLK be slightly longer than the longest CLKOUT trace.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 55 points

    We just need to know what the exact rules are for using one clock (CLKOUT0) to one PCI device and CLKOUT6-to-CLK and which document defines them.  Also, terms like “slightly longer” are vague (is 1 mil longer enough?). 

    This all started with this note on the EVM schematic (which seemed pretty clear … but perhaps was wrong?): 

    “The PCI_FBCLK trace must be 2.5 inches (2500 mils) longer than the length of the other clock signals”

    (note:  PCI_FBCLK is the CLKOUT6-to-CLK signal on the EVM).

     

    Then I think the following confused me in the XIO2001 Implementation Guide (from pg 10 in SCPA045B–August 2009–Revised April 2012) and I think I got confused by the “NOTE” and the diagram.

     

     

     

     

     

    There actually wasn’t that much in the datasheet.

  • 0 in reply to Jeff Brown
    TI__Guru* 76130 points

    Sorry for the confusion,

    The guidelines are:

    The CLKOUT signals going to the PCI downstream devices should be length matched, the maximum mismatch between CLKOUT signals is 250mils.

    If one of the CLKOUT signals is going into an add-in card, that signal should be 2.5 inches shorter that the other CLKOUT signals that don't go to an add-in card.

    The feedback clock signal going from CLKOUT6 to CLK should be longer than the longest CLKOUT signal (yes, 1 mil is longer).

    All the CLKOUT signals should be longer than the longest PCI A/D signal.

    Regards.

  • 0 in reply to Elias Villegas M.
    Intellectual 345 points

    AOK .. that is clear.  Thanks!