TUSB9261 SPI Timing

Hello Brian,

The SPI interface of the TUSB9261 is controlled by the device itself, including the communication with the flash memory and It has been tested with different models of memories. You can see some examples of these tests and its reached frequencies within the TUSB9260 Implementation Guide, secction 10 ( http://www.ti.com/lit/an/slla301c/slla301c.pdf ).

MANUFACTURER     PART NUMBER        DENSITY(kbit)         PAGE SIZE (bytes)                 MAX CLOCK FREQUENCY READ COMMAND (MHz)
Numonyx/ST               M25P05A                    512                            256                                           20 / 25
Numonyx/ST               M25P10A                    1024                          256                                           20 / 25
Atmel                            AT25FS010                1024                          256                                           50
Pflash                          Pm25LV512A             512                            256                                           33
Pflash                          Pm25LV010A             1024                          256                                           33

Regards,

Diego.

Thanks for the quick reply, Diego.  So, does that mean there is no timing diagram available? These parts are old and are generally not available or not recommended for new designs.  I would like to use something current, but need to verify the design.

Regards,

Brian.

Hello Brian,

In order to provide you a better support, I want to know if you are looking for the maximum time for the turn-on cycle, or the best SPI performance, or another specific detail. May be faster to solve if I know What I have to look for.

Regards,

Diego

Hi Diego,

Primarily clock to output valid delay time for SS and Data (and which clock edge this is referenced to), and setup/hold times for input data to clock (and which clock edge this is referenced to).

Thanks,

Brian.

Hello Brian

The SPI interface can operate over a frequency range of 100 kHz to 50 MHz, however, the bootloader uses a fixed frequency of 18.75 MHz. The flash must use a word size of 8 bits and an address length of 24 bits. The program instruction must allow 256 bytes to be written in one operation. The set up time is 53 ns and the hold time is 40 ns. The entire chip is erased by the bootloader prior to programming.

Regards,

Diego.

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