LMH0366 Problem

Chris

Could you please elaborate on the problem that you are having? - Is the PLL failing to lock? - Does this happen at all rates, or just one? - Are you using the crystal reference or are you going referenceless?

Mark

Mark,

The design is referencless,xtal pin tied to ground. HD rates ...seen this with 1080p23 and 1080p60 so both 1.45 and 2.97GHz.

if I put my finger on the loop filter cap (56nF 0402 no ground under , all layers, hard up against reclocker)...The pll seems to go unstable but lock detect pin

does not indicate. Can see SDI jitter goes way up, and anythiing down streeam loses lock due to loss of signal/poor signal quaality. I mention this as may be a clue..

Under normal operation (no finger) occassionally same effect. Seems to be worse at temperature, and some devices seem much worse than others. 

Any ideas appreciated!

Chris

Chris

What is driving the LMH0366?  - Is it possible to send me a snippet of the schematic?

Mark

I have a similar problem. The reclocker works for SD and HD signals but does not lock to 3Gb inputs. The lock detect output toggles with 3Gb signals and the jitter introduced LMH0366 results in the downstream Phabrix SDI analyzer to lose lock. I can verify a 3Gb signal works through the path I am monitoring by shorting the LMH0366 bypass pin to +2.5v. The input is direct coupled from the EQ chip and the output is direct coupled to a SY58609 mux.

I have a very simple circuit, no SPI, all "pin mode" control pins are un-connected and set correctly with internal pull up/down. A 27 MHz crytal is used and oscillating as expected.

I tried an external +2.5v power supply with no difference in performance.

-Jay

Hi Chris and Jay,

One test that you may have done, what happens if we have signal on just one device at a time? Do you see the device lock reliably then?This test may pin point whether this is due to basic lock or interference from other sources.

It seems you have taken precautions in the layout to minimize the VCO noise from adjcent channel. There are two ideas that come to mind:

1). Can we use a small 4.7pF Cap between LF1(pin 22) and VEE(pin21). This will attenuate the VCO noise.

2). Also, is the SPI bus operational ? It would be very helpfull if we can get a memory dump of the registers.

Regards,,nasser

Nasser,

I do not have a signal on the 2nd reclocker (located on the bottom side separated by 8 power/gnd planes) and have disabled this 2nd reclocker by shorting pin 4 to gnd. This alone does not stop the oscillator so I shorted it to gnd. There is no difference in performance. The reclocker under test can not lock to 3Gb signals. I then replaced the 56 nF loop filter cap with a 47 nF cap, no difference.

I probe the LF1 node frequently, this is equivalent to adding capacitance to gnd at this node. Your suggestion of adding a small cap to the LF1 node is counter to the app note describing removal of the gnd plane under these pins and the cap.

I do not use the SPI interface, have a very simple circuit. It works fine for SD and HD but can not lock to 3G.

Do you have customers who have the LMH0366 working with 3Gb signals?

-Jay

Jay

We have several customers who have successful designs, which are in production with the LMH0366 - Nasser will continue to support you to get to the bottom of your issues.

Mark

Nasser,

In the battle of power dissipation I don't think I have enough margin for the LMH0346.. the LMH0366 appears to be my direction of design travel.. This being said.. I've not found any further details from Jay's posting with respect to the 4.7pF cap and it performing the same basic function as ground plane under the Loop Filter..

What is the revised layout recomondations for the LMH0366.

Three SPI register tweaks to increase loop filter bandwidth, from an addional posting, recommended changes to: 0x19, 0x0A, and 0x1C which appear to be "reserved" Is there further documentation available with respect to these and other reserved registers..

My application involves several LMH0366/other reclocker pairs with not much space between them.. I appriciate Marks comments that there have been several customers with successfull implementations.. I woudl like to be one of them...

Dave

Hi Dave,

I am not aware if Jay tried 4.7pF to gnd. I think Jay went back and used LMH0346 that he had been using.

The layout recommendation is outlined in the LMH0366 data sheet. Specifically:

a). Removing GND or VCC under the loop filter or planes under the loop filter Cap.

b). Putting the devices as far apart from one another as possible

c). Isolating or using LC filter on power supply of each individual device

d). Isolating ground planes if possible

e). Using 0201 form factor loop filter cap and putting this as close to the device  as possible

f). If you are using LDO to generate 2.5V, please use high swtching frequency perhaps higher than 2MHz.

These were meant to reduce/attenuate any noise injection into the loop filter.

The register workaround intention is to increase the loop filter bandwidth and enable the device to better track the injected jitter. There are no additional setting.

Regards,,nasser