Hi,
I'm having trouble getting the PHY on the DP83865 to connect to a Gb switch.
I have 3 prototype boards say A, B & C designed for RGMII operation.
A & B the PHY connects fine. PHY on C attempts to connect then fails (but only in RGMII mode!)
This is very repeatable and the same cable and switch port is used on each board in turn, so I'm sure it is a problem with the PCB setup.
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I'm using the DP83865 in the following configuration:
FPGA - DP83865 - termination & magnetics & RJ45. Then 1m of cat5e into a Gb switch.
For these tests I'm tapping into the DP83865 Management Debug interface using an off board mcu.
I'm only interested in getting the PHY to connect at this stage, so the FPGA can be ignored.
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If the straps RGMII_SEL0 and SEL1 are pulled high (i.e. RGMII mode) and a reset applied, then the PHY on boards A & B connect.C repeatedly attempts then fails (switch box lights for ~1s then out for 1s). After a while on board C the 5 status LED's on the DP83865 all flash at ~ 4 times per second.
if the straps RGMII_SEL0 and SEL1 are pulled low (i.e. GMII mode) and a reset applied, then the PHY on all 3 boards connect at 1Gb/s full duplex.
I am determining connection by the light on Gb switch box lighting continuously and also the value of LINK_AN (addr 0x11) bits 4:1.
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This is where its gets a bit stranger...
After establishing a good link:
Board A shows 0x0416 in LINK_AN (i.e. MDI cross over mode) in either RGMII or GMII modes
Board C shows 0x0016 in LINK_AN (i.e. MDI straight mode)in GMII mode (PHY won't connect in RGMII mode)
Using the same cable!
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So my main problems are:
1. Why do the strapping values for RGMII (pins 40, 60) have an effect on the PHY connecting or not? (I was surprised by this since I thought this would only impact the MAC interface.)
2. what is the significance of all 5 status LED's flashing rapidly (I can't see this documented anywhere).
3. After connecting board A shows a cross over on the MDI and board C no crossover on the MDI. Yet it is the same PCB artwork, and the same Cat5e cable and switch port in both tests. Any ideas?
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Any help would be much appreciated!!
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Mark.