- I am using the DS150BR150 to buffer a video FPDLink interface running at SVGA or XGA resolution. So pixel clock at 40MHz or 65MHz and four lanes of data at 7/4*(40MHz or 65MHz). I am trying to reduce EMI emissions of this interface. I was a little suprised at the levels, since LVDS is such a low swing, but it does have some fast edge rates.
I did not find any PCB layout recommendations or decoupling guidelines for the DS10BR150. So I based some of the design on the limited eval board documentation. Many times EMI investigation leads back to layout.
To date, I have tried some common mode chokes without much improvement.
--Brady
