DP83848YB Timing

Gene,

The timing for T2.14.2 in the datasheet is not a typo.  I will try to clarify the intent of the spec.

Data is generated at the falling edge of the RX_CLK and should be sampled at the rising edge by the MAC.  Regarding the transition on RXD_0 / RX_DV occurring before the falling edge of RX_CLK, consider a source synchronous event inside the device.  If the RX_CLK and the RXD_0 / RX_DV edges are generated on the edge of that event, but RX_CLK has a longer output delay to the pin relative to RXD_0 / RX_DV, then RXD_0 / RX_DV will transition first when measured at the pin. 

For an SNI MAC, the key timing will be relative to the rising edge of RX_CLK.  Another way of interpreting the timing in the datasheet is to consider the minimum setup and hold for RXD_0 / RX_DV relative to the rising edge of RX_CLK at the SNI MAC:

• With a 35ns high time on RX_CLK and a -10ns delay relative to the falling edge, the hold time relative to the rising edge of RX_CLK will be 25ns (35ns - 10ns). 
• With a 65ns high time on RX_CLK and a +10ns delay relative to the falling edge, the setup time relative to the rising edge of RX_CLK will be 25ns (100ns - (65ns +10ns)).

As you can see, the timing results in relatively large setup and hold margins.

Patrick