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DP83620 Clock Source with Zero delay buffer

Nithin Mohanan
Prodigy 220 points
Other Parts Discussed in Thread: DP83620

 We are using the seperate DP83620 to interface 2 seperate SFP modules to the iMX287

We are planning follow the below architecture for the PHY chips. Ie; using one zero delay buffer we are planning to give each of the 2 PHY chip and the iMX287 50MHz clock from a single 50MHZ sourse as in image (the image link is given below)

We are using 2 independent channels with different fiber routing.

Can anyone tell me that is there any problem in using  such a configuration??

The optical transceivers we are using are operating at 155Mb/s. The processor will support maximum of 100Mb/s.

If we are following the above scheme do we have to consider additional components like FIFO between the processor and the PHY chip or not.???

Image link:: https://plus.google.com/_/notifications/ngemlink?&emid=COCZn9GhnLUCFcaHTAod4HkAAA&path=/photos/116642735913752502170/albums/5841014683802860145?gpinv=AMIXal-N_a9cQxkTJV7FBXMv-H9U_XQKZBh-LyQdp5-jt6zd4o2gKYkQGIriU-5_wGPeICzLfQ2wTDY5Pg4yfNTHkvIstnGgAPM2L7jg_JljpWZn7VVBA5I&authkey=CNKYwfvApMbMqAE&dt=1359967473362&uob=8:550:0

 


 

  • 0
    TI__Mastermind 31600 points

    Nithin,

    I am not familiar with the Freescale processor so I can't comment on its input requirements for the RMII clock.  However, I can recommend some resources to help you with your design.

    The DP83620 supports RMII master mode (http://www.ti.com/litv/pdf/snla101).  In this mode, a 25MHz crystal can be used as the reference clock source for the device.  The device will output a clock that can be provided to the MAC or to another Phy as its reference clock.  This mode might allow you to simplify your clocking.

    The DP83620 evaluation board schematics (http://www.ti.com/litv/pdf/snlr004) show a possible implementation using a fiber transceiver.  The fiber transceiver shown in the schematic (Avago AFBR-5803) is rated for Fast Ethernet transceivers.  Are your chosen transceivers similar to this component in terms of their specifications?

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 220 points

    Dear Patric,

    Thank u for your reply and the fiber transceiver that we are using is not the same type as that of one that is mentioned in the DP83620 evaluation board we use SFP type optical transceivers which is different from the Avago AFBR-5803. In our design we are planing to use SFP type optical transceiver from peak opticals of data rate 100Mb/s. For that design is it necessary to use external FIFO? can you please confirm it ?

    Nithin M

  • 0 in reply to Nithin Mohanan
    TI__Mastermind 31600 points

    Nithin,

    If you can identify the SFP optical transceiver you plan to use, I will review it for applicability. 

    Regarding the need for a FIFO, I will need some additional detail on your question.  The DP83620 includes a FIFO (also referred to as the elasticity buffer in the datasheet) to handle potential frequency differences between the 50 MHz reference clock and the recovered receive clock.  In most RMII applications, no additional FIFO is needed.  What would be the purpose of the external FIFO and what leads you to consider using a FIFO?

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 220 points

    Patric,

    We are currently considering the optical transceiver from peak opticals (part no : PCSFP-24-14912-12F) which is operating at 155 Mb/s with the ethernet PHy chip DP83620 in 100Mb/s FX mode. For our particular application we need to transfer 120 Bytes in every 1 ms time interval. We have noticed the option of elastic buffer FIFO  in DP83620,  but is that FIFO size is enough for our particular application?? could you please confirm that is there is any need of external FIFO?

  • 0 in reply to Nithin Mohanan
    TI__Mastermind 31600 points

    Nithin,

    I could not find the specifications for the transceiver.  I suggest that you contact the vendor and ask them to confirm that this transceiver is suitable for fast ethernet 100Base-FX applications. 

    Does the concern about the need for an external FIFO stem from the concept that something is needed to bridge between signaling at 155 Mb/s and 100Mb/s?  If so, then there is no need for an external FIFO.  The system will not function at these rates.  Below I will provide more details on the functionality of the Phy in 100Base-FX. 

    In 100Base-FX, the transmit and receive signaling is serialized 5B4B encoded NRZI data at 125 MHz.  This is the data that will be passing between the Phy and the optical transceiver. 

    The Phy will not operate at 155 Mb/s.  The transceiver may be rated to 155 Mb/s, but will not be operated at that rate.  That is why it is important to confirm with the vendor that the chosen transceiver is suitable for 100Base-FX applications. 

    The elasticity buffer FIFO in the Phy accounts for variations between the local clock offset and the far end partner clock offset.  The expectation is that both of these clocks are within 50ppm (parts-per-million) of the nominal reference clock frequency (25MHz or 50MHz).  For clocks that meet this requirement, the elasticity buffer FIFO can accommodate packet sizes larger than the IEEE specified maximum (1514 bytes + 4 bytes CRC).  Please see the RMII section of the datasheet and Table 5, "Supported Packet Sizes ..." for details.  120 bytes packets should not pose any problem for the receiver if the chosen transceiver is suitable for 100Base-FX and the Phy clocks are within 50ppm of the nominal frequency. 

    Please let me know if you have any additional questions or concerns. 

    Patrick

  • 0 in reply to Patrick OFarrell
    Prodigy 220 points

    Patric,

    We have tested and verified that the optical transceiver mentioned above  is suitable for 100Base-FX mode and now everything is clear about  the interfacing between optical transceiver and DP83620 PHY chip.

    Thank You very much for the valuable informations that you have shared with us.

    Nithin M

    SFO Technologies