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DP83630: absolute min of Idd

Other Parts Discussed in Thread: DP83630

Hi

What is Idd for DP83630 when pin RESET_N=0?

When will be absolute min of Idd? I don’t want disconnect Vdd… 

  • We have a power measurement application note (http://www.ti.com/litv/pdf/snla089a) that details power consumption in different modes of operation.  It does not include data for reset, but it does include data for power down mode.  According to the power measurement application note, the device should draw approximately 7mA from the 3.3V supply in power down mode. 

    The device can be put into power down mode by asserting the PWRDOWN low (PWRDOWN/INTN = 0V) or by setting the the Power Down bit (bit 11) in the Basic Mode Control Register (BMCR), address 0x00.  The power dissipation in power down mode should be comparable to reset, but using power down mode does have advantages when it comes to configuration:

    • When RESET_N is asserted, the device configuration will be reset.  Any register configuration that had been performed would need to be repeated when the device is released from reset. 
    • When PWRDOWN/INTN is asserted, the device configuration will be maintained.  No additional register configuration will be required when the device is taken out of power down mode.

    Patrick

  • Patrick, thank You

    In this “AN-1540” minimum current – is 7mA.

    10mA (for DP83630) in Power Down – is very large for device in mobile mode when Ethernet isn’t used. Disconnect all power of DP83630 in this mode is inconveniently for me…

    What will be, if I set mode “Power Down”, switch off clock (pin 34 “X1” = 0 ) and disconnect only an analog power from DP83630 (pin 19 “ANA33VDD”) and central tap of transformer?

    Alexander

  • Alexander,

    What is your target power for the DP83630 when Ethernet is not being used?  Could you share some additional details on the application?

    We don't have any data on the specific configuration that you suggested, but I will see what we can do.  Powering down independent supply pins may not be recommended.  I will inquire about this with the design team.

    Patrick

  • Alexander,

    After performing some simple lab experiments and discussing this with the design team, I believe the low current consumption achieved by asserting the power down pin and stopping the X1 reference clock is the best reasonable minimum.  Powering down independent supplies is not recommended.  It would be better to power down the entire chip by powering down all the supplies. 

    Patrick

  • Patrick, thank You for good job!

    What Idd current in this mode?

    Alexander

  • Alexander,

    In this mode, with the Power Down pin asserted and the X1 reference clock stopped, the Idd was <5mA. 

    Patrick

  • 5mA - it is big. I will need to switch off power...

    Thank You